^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (c) 2018-2019, The Linux Foundation. All rights reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include <linux/clk-provider.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/regmap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/reset-controller.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <dt-bindings/clock/qcom,dispcc-sdm845.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include "clk-alpha-pll.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include "clk-branch.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include "clk-rcg.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include "clk-regmap-divider.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include "common.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include "gdsc.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include "reset.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) P_BI_TCXO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) P_CORE_BI_PLL_TEST_SE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) P_DISP_CC_PLL0_OUT_MAIN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) P_DSI0_PHY_PLL_OUT_BYTECLK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) P_DSI0_PHY_PLL_OUT_DSICLK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) P_DSI1_PHY_PLL_OUT_BYTECLK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) P_DSI1_PHY_PLL_OUT_DSICLK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) P_GPLL0_OUT_MAIN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) P_GPLL0_OUT_MAIN_DIV,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) P_DP_PHY_PLL_LINK_CLK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) P_DP_PHY_PLL_VCO_DIV_CLK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) static const struct parent_map disp_cc_parent_map_0[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) { P_BI_TCXO, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) { P_DSI0_PHY_PLL_OUT_BYTECLK, 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) { P_DSI1_PHY_PLL_OUT_BYTECLK, 2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) { P_CORE_BI_PLL_TEST_SE, 7 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) static const char * const disp_cc_parent_names_0[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) "bi_tcxo",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) "dsi0_phy_pll_out_byteclk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) "dsi1_phy_pll_out_byteclk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) "core_bi_pll_test_se",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) static const struct parent_map disp_cc_parent_map_1[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) { P_BI_TCXO, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) { P_DP_PHY_PLL_LINK_CLK, 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) { P_DP_PHY_PLL_VCO_DIV_CLK, 2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) { P_CORE_BI_PLL_TEST_SE, 7 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) static const char * const disp_cc_parent_names_1[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) "bi_tcxo",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) "dp_link_clk_divsel_ten",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) "dp_vco_divided_clk_src_mux",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) "core_bi_pll_test_se",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) static const struct parent_map disp_cc_parent_map_2[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) { P_BI_TCXO, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) { P_CORE_BI_PLL_TEST_SE, 7 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) static const char * const disp_cc_parent_names_2[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) "bi_tcxo",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) "core_bi_pll_test_se",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) static const struct parent_map disp_cc_parent_map_3[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) { P_BI_TCXO, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) { P_DISP_CC_PLL0_OUT_MAIN, 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) { P_GPLL0_OUT_MAIN, 4 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) { P_GPLL0_OUT_MAIN_DIV, 5 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) { P_CORE_BI_PLL_TEST_SE, 7 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) static const char * const disp_cc_parent_names_3[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) "bi_tcxo",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) "disp_cc_pll0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) "gcc_disp_gpll0_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) "gcc_disp_gpll0_div_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) "core_bi_pll_test_se",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) static const struct parent_map disp_cc_parent_map_4[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) { P_BI_TCXO, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) { P_DSI0_PHY_PLL_OUT_DSICLK, 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) { P_DSI1_PHY_PLL_OUT_DSICLK, 2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) { P_CORE_BI_PLL_TEST_SE, 7 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) static const char * const disp_cc_parent_names_4[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) "bi_tcxo",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) "dsi0_phy_pll_out_dsiclk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) "dsi1_phy_pll_out_dsiclk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) "core_bi_pll_test_se",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) static struct clk_alpha_pll disp_cc_pll0 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) .offset = 0x0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) .name = "disp_cc_pll0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) .parent_names = (const char *[]){ "bi_tcxo" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) .ops = &clk_alpha_pll_fabia_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) /* Return the HW recalc rate for idle use case */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) static struct clk_rcg2 disp_cc_mdss_byte0_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) .cmd_rcgr = 0x20d0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) .mnd_width = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) .parent_map = disp_cc_parent_map_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) .name = "disp_cc_mdss_byte0_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) .parent_names = disp_cc_parent_names_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) .num_parents = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) .ops = &clk_byte2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) /* Return the HW recalc rate for idle use case */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) static struct clk_rcg2 disp_cc_mdss_byte1_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) .cmd_rcgr = 0x20ec,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) .mnd_width = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) .parent_map = disp_cc_parent_map_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) .name = "disp_cc_mdss_byte1_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) .parent_names = disp_cc_parent_names_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) .num_parents = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) .ops = &clk_byte2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) static const struct freq_tbl ftbl_disp_cc_mdss_dp_aux_clk_src[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) F(19200000, P_BI_TCXO, 1, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) static struct clk_rcg2 disp_cc_mdss_dp_aux_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) .cmd_rcgr = 0x219c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) .mnd_width = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) .parent_map = disp_cc_parent_map_2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) .freq_tbl = ftbl_disp_cc_mdss_dp_aux_clk_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) .name = "disp_cc_mdss_dp_aux_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) .parent_names = disp_cc_parent_names_2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) .num_parents = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) static struct clk_rcg2 disp_cc_mdss_dp_crypto_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) .cmd_rcgr = 0x2154,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) .mnd_width = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) .parent_map = disp_cc_parent_map_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) .name = "disp_cc_mdss_dp_crypto_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) .parent_names = disp_cc_parent_names_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) .num_parents = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) .ops = &clk_byte2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) static struct clk_rcg2 disp_cc_mdss_dp_link_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) .cmd_rcgr = 0x2138,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) .mnd_width = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) .parent_map = disp_cc_parent_map_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) .name = "disp_cc_mdss_dp_link_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) .parent_names = disp_cc_parent_names_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) .num_parents = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) .ops = &clk_byte2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) static struct clk_rcg2 disp_cc_mdss_dp_pixel1_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) .cmd_rcgr = 0x2184,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) .mnd_width = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) .parent_map = disp_cc_parent_map_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) .name = "disp_cc_mdss_dp_pixel1_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) .parent_names = disp_cc_parent_names_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) .num_parents = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) .ops = &clk_dp_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) static struct clk_rcg2 disp_cc_mdss_dp_pixel_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) .cmd_rcgr = 0x216c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) .mnd_width = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) .parent_map = disp_cc_parent_map_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) .name = "disp_cc_mdss_dp_pixel_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) .parent_names = disp_cc_parent_names_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) .num_parents = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) .ops = &clk_dp_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) static const struct freq_tbl ftbl_disp_cc_mdss_esc0_clk_src[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) F(19200000, P_BI_TCXO, 1, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) static struct clk_rcg2 disp_cc_mdss_esc0_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) .cmd_rcgr = 0x2108,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) .mnd_width = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) .parent_map = disp_cc_parent_map_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) .freq_tbl = ftbl_disp_cc_mdss_esc0_clk_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) .name = "disp_cc_mdss_esc0_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) .parent_names = disp_cc_parent_names_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) .num_parents = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) static struct clk_rcg2 disp_cc_mdss_esc1_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) .cmd_rcgr = 0x2120,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) .mnd_width = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) .parent_map = disp_cc_parent_map_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) .freq_tbl = ftbl_disp_cc_mdss_esc0_clk_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) .name = "disp_cc_mdss_esc1_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) .parent_names = disp_cc_parent_names_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) .num_parents = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) static const struct freq_tbl ftbl_disp_cc_mdss_mdp_clk_src[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) F(19200000, P_BI_TCXO, 1, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) F(85714286, P_GPLL0_OUT_MAIN, 7, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) F(150000000, P_GPLL0_OUT_MAIN, 4, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) F(171428571, P_GPLL0_OUT_MAIN, 3.5, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) F(300000000, P_GPLL0_OUT_MAIN, 2, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) F(344000000, P_DISP_CC_PLL0_OUT_MAIN, 2.5, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) F(430000000, P_DISP_CC_PLL0_OUT_MAIN, 2, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) static struct clk_rcg2 disp_cc_mdss_mdp_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) .cmd_rcgr = 0x2088,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) .mnd_width = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) .parent_map = disp_cc_parent_map_3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) .freq_tbl = ftbl_disp_cc_mdss_mdp_clk_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) .name = "disp_cc_mdss_mdp_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) .parent_names = disp_cc_parent_names_3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) .num_parents = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) .ops = &clk_rcg2_shared_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) /* Return the HW recalc rate for idle use case */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) static struct clk_rcg2 disp_cc_mdss_pclk0_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) .cmd_rcgr = 0x2058,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) .mnd_width = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) .parent_map = disp_cc_parent_map_4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) .name = "disp_cc_mdss_pclk0_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) .parent_names = disp_cc_parent_names_4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) .num_parents = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) .ops = &clk_pixel_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) /* Return the HW recalc rate for idle use case */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) static struct clk_rcg2 disp_cc_mdss_pclk1_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) .cmd_rcgr = 0x2070,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) .mnd_width = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) .parent_map = disp_cc_parent_map_4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) .name = "disp_cc_mdss_pclk1_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) .parent_names = disp_cc_parent_names_4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) .num_parents = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) .ops = &clk_pixel_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) static const struct freq_tbl ftbl_disp_cc_mdss_rot_clk_src[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) F(19200000, P_BI_TCXO, 1, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) F(171428571, P_GPLL0_OUT_MAIN, 3.5, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) F(300000000, P_GPLL0_OUT_MAIN, 2, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) F(344000000, P_DISP_CC_PLL0_OUT_MAIN, 2.5, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) F(430000000, P_DISP_CC_PLL0_OUT_MAIN, 2, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) static struct clk_rcg2 disp_cc_mdss_rot_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) .cmd_rcgr = 0x20a0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) .mnd_width = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) .parent_map = disp_cc_parent_map_3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) .freq_tbl = ftbl_disp_cc_mdss_rot_clk_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) .name = "disp_cc_mdss_rot_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) .parent_names = disp_cc_parent_names_3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) .num_parents = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) .ops = &clk_rcg2_shared_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) static struct clk_rcg2 disp_cc_mdss_vsync_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) .cmd_rcgr = 0x20b8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) .mnd_width = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) .parent_map = disp_cc_parent_map_2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) .freq_tbl = ftbl_disp_cc_mdss_esc0_clk_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) .name = "disp_cc_mdss_vsync_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) .parent_names = disp_cc_parent_names_2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) .num_parents = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) static struct clk_branch disp_cc_mdss_ahb_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) .halt_reg = 0x4004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) .halt_check = BRANCH_HALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) .enable_reg = 0x4004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) .name = "disp_cc_mdss_ahb_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) static struct clk_branch disp_cc_mdss_axi_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) .halt_reg = 0x4008,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) .halt_check = BRANCH_HALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) .enable_reg = 0x4008,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) .name = "disp_cc_mdss_axi_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) /* Return the HW recalc rate for idle use case */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) static struct clk_branch disp_cc_mdss_byte0_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) .halt_reg = 0x2028,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) .halt_check = BRANCH_HALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) .enable_reg = 0x2028,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) .name = "disp_cc_mdss_byte0_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) "disp_cc_mdss_byte0_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) /* Return the HW recalc rate for idle use case */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) static struct clk_regmap_div disp_cc_mdss_byte0_div_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) .reg = 0x20e8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) .shift = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) .width = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) .name = "disp_cc_mdss_byte0_div_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) "disp_cc_mdss_byte0_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) .ops = &clk_regmap_div_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) /* Return the HW recalc rate for idle use case */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) static struct clk_branch disp_cc_mdss_byte0_intf_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) .halt_reg = 0x202c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) .halt_check = BRANCH_HALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) .enable_reg = 0x202c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) .name = "disp_cc_mdss_byte0_intf_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) "disp_cc_mdss_byte0_div_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) /* Return the HW recalc rate for idle use case */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) static struct clk_branch disp_cc_mdss_byte1_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) .halt_reg = 0x2030,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) .halt_check = BRANCH_HALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) .enable_reg = 0x2030,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) .name = "disp_cc_mdss_byte1_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) "disp_cc_mdss_byte1_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) /* Return the HW recalc rate for idle use case */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) static struct clk_regmap_div disp_cc_mdss_byte1_div_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) .reg = 0x2104,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) .shift = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) .width = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) .name = "disp_cc_mdss_byte1_div_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) "disp_cc_mdss_byte1_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) .ops = &clk_regmap_div_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) /* Return the HW recalc rate for idle use case */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) static struct clk_branch disp_cc_mdss_byte1_intf_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) .halt_reg = 0x2034,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) .halt_check = BRANCH_HALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) .enable_reg = 0x2034,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) .name = "disp_cc_mdss_byte1_intf_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) "disp_cc_mdss_byte1_div_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) static struct clk_branch disp_cc_mdss_dp_aux_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) .halt_reg = 0x2054,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) .halt_check = BRANCH_HALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) .enable_reg = 0x2054,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) .name = "disp_cc_mdss_dp_aux_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) "disp_cc_mdss_dp_aux_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) static struct clk_branch disp_cc_mdss_dp_crypto_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) .halt_reg = 0x2048,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) .halt_check = BRANCH_HALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) .enable_reg = 0x2048,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) .name = "disp_cc_mdss_dp_crypto_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) "disp_cc_mdss_dp_crypto_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) static struct clk_branch disp_cc_mdss_dp_link_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) .halt_reg = 0x2040,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) .halt_check = BRANCH_HALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) .enable_reg = 0x2040,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) .name = "disp_cc_mdss_dp_link_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) "disp_cc_mdss_dp_link_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) /* reset state of disp_cc_mdss_dp_link_div_clk_src divider is 0x3 (div 4) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) static struct clk_branch disp_cc_mdss_dp_link_intf_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) .halt_reg = 0x2044,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) .halt_check = BRANCH_HALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) .enable_reg = 0x2044,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) .name = "disp_cc_mdss_dp_link_intf_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) "disp_cc_mdss_dp_link_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) static struct clk_branch disp_cc_mdss_dp_pixel1_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) .halt_reg = 0x2050,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) .halt_check = BRANCH_HALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) .enable_reg = 0x2050,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) .name = "disp_cc_mdss_dp_pixel1_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) "disp_cc_mdss_dp_pixel1_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) static struct clk_branch disp_cc_mdss_dp_pixel_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) .halt_reg = 0x204c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) .halt_check = BRANCH_HALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) .enable_reg = 0x204c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) .name = "disp_cc_mdss_dp_pixel_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) "disp_cc_mdss_dp_pixel_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) static struct clk_branch disp_cc_mdss_esc0_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) .halt_reg = 0x2038,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) .halt_check = BRANCH_HALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) .enable_reg = 0x2038,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) .name = "disp_cc_mdss_esc0_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) "disp_cc_mdss_esc0_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) static struct clk_branch disp_cc_mdss_esc1_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) .halt_reg = 0x203c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) .halt_check = BRANCH_HALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) .enable_reg = 0x203c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) .name = "disp_cc_mdss_esc1_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) "disp_cc_mdss_esc1_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) static struct clk_branch disp_cc_mdss_mdp_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) .halt_reg = 0x200c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) .halt_check = BRANCH_HALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) .enable_reg = 0x200c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) .name = "disp_cc_mdss_mdp_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) "disp_cc_mdss_mdp_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) static struct clk_branch disp_cc_mdss_mdp_lut_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) .halt_reg = 0x201c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) .halt_check = BRANCH_HALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) .enable_reg = 0x201c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) .name = "disp_cc_mdss_mdp_lut_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) "disp_cc_mdss_mdp_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) /* Return the HW recalc rate for idle use case */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) static struct clk_branch disp_cc_mdss_pclk0_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) .halt_reg = 0x2004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) .halt_check = BRANCH_HALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) .enable_reg = 0x2004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) .name = "disp_cc_mdss_pclk0_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) "disp_cc_mdss_pclk0_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) /* Return the HW recalc rate for idle use case */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) static struct clk_branch disp_cc_mdss_pclk1_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) .halt_reg = 0x2008,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) .halt_check = BRANCH_HALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) .enable_reg = 0x2008,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) .name = "disp_cc_mdss_pclk1_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) "disp_cc_mdss_pclk1_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) static struct clk_branch disp_cc_mdss_rot_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) .halt_reg = 0x2014,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) .halt_check = BRANCH_HALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) .enable_reg = 0x2014,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) .name = "disp_cc_mdss_rot_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) "disp_cc_mdss_rot_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) static struct clk_branch disp_cc_mdss_rscc_ahb_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) .halt_reg = 0x5004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) .halt_check = BRANCH_HALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) .enable_reg = 0x5004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) .name = "disp_cc_mdss_rscc_ahb_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) static struct clk_branch disp_cc_mdss_rscc_vsync_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) .halt_reg = 0x5008,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) .halt_check = BRANCH_HALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) .enable_reg = 0x5008,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) .name = "disp_cc_mdss_rscc_vsync_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) "disp_cc_mdss_vsync_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) static struct clk_branch disp_cc_mdss_vsync_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) .halt_reg = 0x2024,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) .halt_check = BRANCH_HALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) .enable_reg = 0x2024,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) .name = "disp_cc_mdss_vsync_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) "disp_cc_mdss_vsync_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) static struct gdsc mdss_gdsc = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) .gdscr = 0x3000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) .pd = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) .name = "mdss_gdsc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) .pwrsts = PWRSTS_OFF_ON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) .flags = HW_CTRL | POLL_CFG_GDSCR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) static struct clk_regmap *disp_cc_sdm845_clocks[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) [DISP_CC_MDSS_AHB_CLK] = &disp_cc_mdss_ahb_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) [DISP_CC_MDSS_AXI_CLK] = &disp_cc_mdss_axi_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) [DISP_CC_MDSS_BYTE0_CLK] = &disp_cc_mdss_byte0_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) [DISP_CC_MDSS_BYTE0_CLK_SRC] = &disp_cc_mdss_byte0_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) [DISP_CC_MDSS_BYTE0_INTF_CLK] = &disp_cc_mdss_byte0_intf_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) [DISP_CC_MDSS_BYTE0_DIV_CLK_SRC] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) &disp_cc_mdss_byte0_div_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) [DISP_CC_MDSS_BYTE1_CLK] = &disp_cc_mdss_byte1_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) [DISP_CC_MDSS_BYTE1_CLK_SRC] = &disp_cc_mdss_byte1_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) [DISP_CC_MDSS_BYTE1_INTF_CLK] = &disp_cc_mdss_byte1_intf_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) [DISP_CC_MDSS_BYTE1_DIV_CLK_SRC] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) &disp_cc_mdss_byte1_div_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) [DISP_CC_MDSS_DP_AUX_CLK] = &disp_cc_mdss_dp_aux_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) [DISP_CC_MDSS_DP_AUX_CLK_SRC] = &disp_cc_mdss_dp_aux_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) [DISP_CC_MDSS_DP_CRYPTO_CLK] = &disp_cc_mdss_dp_crypto_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) [DISP_CC_MDSS_DP_CRYPTO_CLK_SRC] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) &disp_cc_mdss_dp_crypto_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) [DISP_CC_MDSS_DP_LINK_CLK] = &disp_cc_mdss_dp_link_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) [DISP_CC_MDSS_DP_LINK_CLK_SRC] = &disp_cc_mdss_dp_link_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) [DISP_CC_MDSS_DP_LINK_INTF_CLK] = &disp_cc_mdss_dp_link_intf_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) [DISP_CC_MDSS_DP_PIXEL1_CLK] = &disp_cc_mdss_dp_pixel1_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) [DISP_CC_MDSS_DP_PIXEL1_CLK_SRC] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) &disp_cc_mdss_dp_pixel1_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) [DISP_CC_MDSS_DP_PIXEL_CLK] = &disp_cc_mdss_dp_pixel_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) [DISP_CC_MDSS_DP_PIXEL_CLK_SRC] = &disp_cc_mdss_dp_pixel_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) [DISP_CC_MDSS_ESC0_CLK] = &disp_cc_mdss_esc0_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) [DISP_CC_MDSS_ESC0_CLK_SRC] = &disp_cc_mdss_esc0_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) [DISP_CC_MDSS_ESC1_CLK] = &disp_cc_mdss_esc1_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) [DISP_CC_MDSS_ESC1_CLK_SRC] = &disp_cc_mdss_esc1_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) [DISP_CC_MDSS_MDP_CLK] = &disp_cc_mdss_mdp_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) [DISP_CC_MDSS_MDP_CLK_SRC] = &disp_cc_mdss_mdp_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) [DISP_CC_MDSS_MDP_LUT_CLK] = &disp_cc_mdss_mdp_lut_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) [DISP_CC_MDSS_PCLK0_CLK] = &disp_cc_mdss_pclk0_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) [DISP_CC_MDSS_PCLK0_CLK_SRC] = &disp_cc_mdss_pclk0_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) [DISP_CC_MDSS_PCLK1_CLK] = &disp_cc_mdss_pclk1_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) [DISP_CC_MDSS_PCLK1_CLK_SRC] = &disp_cc_mdss_pclk1_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) [DISP_CC_MDSS_ROT_CLK] = &disp_cc_mdss_rot_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) [DISP_CC_MDSS_ROT_CLK_SRC] = &disp_cc_mdss_rot_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) [DISP_CC_MDSS_RSCC_AHB_CLK] = &disp_cc_mdss_rscc_ahb_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) [DISP_CC_MDSS_RSCC_VSYNC_CLK] = &disp_cc_mdss_rscc_vsync_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) [DISP_CC_MDSS_VSYNC_CLK] = &disp_cc_mdss_vsync_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) [DISP_CC_MDSS_VSYNC_CLK_SRC] = &disp_cc_mdss_vsync_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) [DISP_CC_PLL0] = &disp_cc_pll0.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) static const struct qcom_reset_map disp_cc_sdm845_resets[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) [DISP_CC_MDSS_RSCC_BCR] = { 0x5000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) static struct gdsc *disp_cc_sdm845_gdscs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) [MDSS_GDSC] = &mdss_gdsc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) static const struct regmap_config disp_cc_sdm845_regmap_config = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) .reg_bits = 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) .reg_stride = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) .val_bits = 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) .max_register = 0x10000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) .fast_io = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) static const struct qcom_cc_desc disp_cc_sdm845_desc = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) .config = &disp_cc_sdm845_regmap_config,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) .clks = disp_cc_sdm845_clocks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) .num_clks = ARRAY_SIZE(disp_cc_sdm845_clocks),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) .resets = disp_cc_sdm845_resets,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) .num_resets = ARRAY_SIZE(disp_cc_sdm845_resets),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) .gdscs = disp_cc_sdm845_gdscs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) .num_gdscs = ARRAY_SIZE(disp_cc_sdm845_gdscs),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) static const struct of_device_id disp_cc_sdm845_match_table[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) { .compatible = "qcom,sdm845-dispcc" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) MODULE_DEVICE_TABLE(of, disp_cc_sdm845_match_table);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) static int disp_cc_sdm845_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) struct regmap *regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) struct alpha_pll_config disp_cc_pll0_config = {};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) regmap = qcom_cc_map(pdev, &disp_cc_sdm845_desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) if (IS_ERR(regmap))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) return PTR_ERR(regmap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) disp_cc_pll0_config.l = 0x2c;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) disp_cc_pll0_config.alpha = 0xcaaa;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) clk_fabia_pll_configure(&disp_cc_pll0, regmap, &disp_cc_pll0_config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) /* Enable hardware clock gating for DSI and MDP clocks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) regmap_update_bits(regmap, 0x8000, 0x7f0, 0x7f0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) return qcom_cc_really_probe(pdev, &disp_cc_sdm845_desc, regmap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) static struct platform_driver disp_cc_sdm845_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) .probe = disp_cc_sdm845_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) .name = "disp_cc-sdm845",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) .of_match_table = disp_cc_sdm845_match_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) .sync_state = clk_sync_state,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) static int __init disp_cc_sdm845_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) return platform_driver_register(&disp_cc_sdm845_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) subsys_initcall(disp_cc_sdm845_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) static void __exit disp_cc_sdm845_exit(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) platform_driver_unregister(&disp_cc_sdm845_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) module_exit(disp_cc_sdm845_exit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) MODULE_LICENSE("GPL v2");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) MODULE_DESCRIPTION("QTI DISPCC SDM845 Driver");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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