^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (c) 2019, The Linux Foundation. All rights reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) #include <linux/clk-provider.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/regmap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <dt-bindings/clock/qcom,dispcc-sc7180.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include "clk-alpha-pll.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include "clk-branch.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include "clk-rcg.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include "clk-regmap-divider.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include "common.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include "gdsc.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) P_BI_TCXO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) P_CHIP_SLEEP_CLK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) P_CORE_BI_PLL_TEST_SE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) P_DISP_CC_PLL0_OUT_EVEN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) P_DISP_CC_PLL0_OUT_MAIN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) P_DP_PHY_PLL_LINK_CLK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) P_DP_PHY_PLL_VCO_DIV_CLK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) P_DSI0_PHY_PLL_OUT_BYTECLK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) P_DSI0_PHY_PLL_OUT_DSICLK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) P_GPLL0_OUT_MAIN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) static const struct pll_vco fabia_vco[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) { 249600000, 2000000000, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) static struct clk_alpha_pll disp_cc_pll0 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) .offset = 0x0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) .vco_table = fabia_vco,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) .num_vco = ARRAY_SIZE(fabia_vco),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) .name = "disp_cc_pll0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) .parent_data = &(const struct clk_parent_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) .fw_name = "bi_tcxo",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) .ops = &clk_alpha_pll_fabia_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) static const struct clk_div_table post_div_table_disp_cc_pll0_out_even[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) { 0x0, 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) static struct clk_alpha_pll_postdiv disp_cc_pll0_out_even = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) .offset = 0x0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) .post_div_shift = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) .post_div_table = post_div_table_disp_cc_pll0_out_even,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) .num_post_div = ARRAY_SIZE(post_div_table_disp_cc_pll0_out_even),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) .width = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) .name = "disp_cc_pll0_out_even",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) .parent_data = &(const struct clk_parent_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) .hw = &disp_cc_pll0.clkr.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) .ops = &clk_alpha_pll_postdiv_fabia_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) static const struct parent_map disp_cc_parent_map_0[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) { P_BI_TCXO, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) static const struct clk_parent_data disp_cc_parent_data_0[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) { .fw_name = "bi_tcxo" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) static const struct parent_map disp_cc_parent_map_1[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) { P_BI_TCXO, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) { P_DP_PHY_PLL_LINK_CLK, 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) { P_DP_PHY_PLL_VCO_DIV_CLK, 2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) static const struct clk_parent_data disp_cc_parent_data_1[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) { .fw_name = "bi_tcxo" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) { .fw_name = "dp_phy_pll_link_clk" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) { .fw_name = "dp_phy_pll_vco_div_clk" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) static const struct parent_map disp_cc_parent_map_2[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) { P_BI_TCXO, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) { P_DSI0_PHY_PLL_OUT_BYTECLK, 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) static const struct clk_parent_data disp_cc_parent_data_2[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) { .fw_name = "bi_tcxo" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) { .fw_name = "dsi0_phy_pll_out_byteclk" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) static const struct parent_map disp_cc_parent_map_3[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) { P_BI_TCXO, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) { P_DISP_CC_PLL0_OUT_MAIN, 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) { P_GPLL0_OUT_MAIN, 4 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) { P_DISP_CC_PLL0_OUT_EVEN, 5 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) static const struct clk_parent_data disp_cc_parent_data_3[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) { .fw_name = "bi_tcxo" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) { .hw = &disp_cc_pll0.clkr.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) { .fw_name = "gcc_disp_gpll0_clk_src" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) { .hw = &disp_cc_pll0_out_even.clkr.hw },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) static const struct parent_map disp_cc_parent_map_4[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) { P_BI_TCXO, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) { P_GPLL0_OUT_MAIN, 4 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) static const struct clk_parent_data disp_cc_parent_data_4[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) { .fw_name = "bi_tcxo" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) { .fw_name = "gcc_disp_gpll0_clk_src" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) static const struct parent_map disp_cc_parent_map_5[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) { P_BI_TCXO, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) { P_DSI0_PHY_PLL_OUT_DSICLK, 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) static const struct clk_parent_data disp_cc_parent_data_5[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) { .fw_name = "bi_tcxo" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) { .fw_name = "dsi0_phy_pll_out_dsiclk" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) static const struct freq_tbl ftbl_disp_cc_mdss_ahb_clk_src[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) F(19200000, P_BI_TCXO, 1, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) F(37500000, P_GPLL0_OUT_MAIN, 16, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) F(75000000, P_GPLL0_OUT_MAIN, 8, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) static struct clk_rcg2 disp_cc_mdss_ahb_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) .cmd_rcgr = 0x22bc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) .mnd_width = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) .parent_map = disp_cc_parent_map_4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) .freq_tbl = ftbl_disp_cc_mdss_ahb_clk_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) .name = "disp_cc_mdss_ahb_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) .parent_data = disp_cc_parent_data_4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) .num_parents = ARRAY_SIZE(disp_cc_parent_data_4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) .ops = &clk_rcg2_shared_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) static struct clk_rcg2 disp_cc_mdss_byte0_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) .cmd_rcgr = 0x2110,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) .mnd_width = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) .parent_map = disp_cc_parent_map_2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) .name = "disp_cc_mdss_byte0_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) .parent_data = disp_cc_parent_data_2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) .num_parents = ARRAY_SIZE(disp_cc_parent_data_2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) .ops = &clk_byte2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) static const struct freq_tbl ftbl_disp_cc_mdss_dp_aux_clk_src[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) F(19200000, P_BI_TCXO, 1, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) static struct clk_rcg2 disp_cc_mdss_dp_aux_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) .cmd_rcgr = 0x21dc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) .mnd_width = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) .parent_map = disp_cc_parent_map_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) .freq_tbl = ftbl_disp_cc_mdss_dp_aux_clk_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) .name = "disp_cc_mdss_dp_aux_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) .parent_data = disp_cc_parent_data_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) .num_parents = ARRAY_SIZE(disp_cc_parent_data_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) static struct clk_rcg2 disp_cc_mdss_dp_crypto_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) .cmd_rcgr = 0x2194,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) .mnd_width = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) .parent_map = disp_cc_parent_map_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) .name = "disp_cc_mdss_dp_crypto_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) .parent_data = disp_cc_parent_data_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) .num_parents = ARRAY_SIZE(disp_cc_parent_data_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) .ops = &clk_byte2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) static struct clk_rcg2 disp_cc_mdss_dp_link_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) .cmd_rcgr = 0x2178,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) .mnd_width = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) .parent_map = disp_cc_parent_map_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) .name = "disp_cc_mdss_dp_link_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) .parent_data = disp_cc_parent_data_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) .num_parents = ARRAY_SIZE(disp_cc_parent_data_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) .ops = &clk_byte2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) static struct clk_rcg2 disp_cc_mdss_dp_pixel_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) .cmd_rcgr = 0x21ac,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) .mnd_width = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) .parent_map = disp_cc_parent_map_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) .name = "disp_cc_mdss_dp_pixel_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) .parent_data = disp_cc_parent_data_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) .num_parents = ARRAY_SIZE(disp_cc_parent_data_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) .ops = &clk_dp_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) static struct clk_rcg2 disp_cc_mdss_esc0_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) .cmd_rcgr = 0x2148,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) .mnd_width = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) .parent_map = disp_cc_parent_map_2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) .freq_tbl = ftbl_disp_cc_mdss_dp_aux_clk_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) .name = "disp_cc_mdss_esc0_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) .parent_data = disp_cc_parent_data_2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) .num_parents = ARRAY_SIZE(disp_cc_parent_data_2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) static const struct freq_tbl ftbl_disp_cc_mdss_mdp_clk_src[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) F(19200000, P_BI_TCXO, 1, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) F(300000000, P_GPLL0_OUT_MAIN, 2, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) F(345000000, P_DISP_CC_PLL0_OUT_MAIN, 4, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) F(460000000, P_DISP_CC_PLL0_OUT_MAIN, 3, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) static struct clk_rcg2 disp_cc_mdss_mdp_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) .cmd_rcgr = 0x20c8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) .mnd_width = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) .parent_map = disp_cc_parent_map_3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) .freq_tbl = ftbl_disp_cc_mdss_mdp_clk_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) .name = "disp_cc_mdss_mdp_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) .parent_data = disp_cc_parent_data_3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) .num_parents = ARRAY_SIZE(disp_cc_parent_data_3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) .ops = &clk_rcg2_shared_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) static struct clk_rcg2 disp_cc_mdss_pclk0_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) .cmd_rcgr = 0x2098,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) .mnd_width = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) .parent_map = disp_cc_parent_map_5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) .name = "disp_cc_mdss_pclk0_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) .parent_data = disp_cc_parent_data_5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) .num_parents = ARRAY_SIZE(disp_cc_parent_data_5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) .ops = &clk_pixel_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) static struct clk_rcg2 disp_cc_mdss_rot_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) .cmd_rcgr = 0x20e0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) .mnd_width = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) .parent_map = disp_cc_parent_map_3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) .freq_tbl = ftbl_disp_cc_mdss_mdp_clk_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) .name = "disp_cc_mdss_rot_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) .parent_data = disp_cc_parent_data_3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) .num_parents = ARRAY_SIZE(disp_cc_parent_data_3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) .ops = &clk_rcg2_shared_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) static struct clk_rcg2 disp_cc_mdss_vsync_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) .cmd_rcgr = 0x20f8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) .mnd_width = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) .parent_map = disp_cc_parent_map_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) .freq_tbl = ftbl_disp_cc_mdss_dp_aux_clk_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) .name = "disp_cc_mdss_vsync_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) .parent_data = disp_cc_parent_data_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) .num_parents = ARRAY_SIZE(disp_cc_parent_data_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) .ops = &clk_rcg2_shared_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) static struct clk_branch disp_cc_mdss_ahb_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) .halt_reg = 0x2080,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) .halt_check = BRANCH_HALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) .enable_reg = 0x2080,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) .name = "disp_cc_mdss_ahb_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) .parent_data = &(const struct clk_parent_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) .hw = &disp_cc_mdss_ahb_clk_src.clkr.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) static struct clk_branch disp_cc_mdss_byte0_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) .halt_reg = 0x2028,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) .halt_check = BRANCH_HALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) .enable_reg = 0x2028,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) .name = "disp_cc_mdss_byte0_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) .parent_data = &(const struct clk_parent_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) .hw = &disp_cc_mdss_byte0_clk_src.clkr.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) static struct clk_regmap_div disp_cc_mdss_byte0_div_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) .reg = 0x2128,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) .shift = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) .width = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) .clkr.hw.init = &(struct clk_init_data) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) .name = "disp_cc_mdss_byte0_div_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) .parent_data = &(const struct clk_parent_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) .hw = &disp_cc_mdss_byte0_clk_src.clkr.hw
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) .ops = &clk_regmap_div_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) static struct clk_regmap_div disp_cc_mdss_dp_link_div_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) .reg = 0x2190,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) .shift = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) .width = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) .clkr.hw.init = &(struct clk_init_data) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) .name = "disp_cc_mdss_dp_link_div_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) .parent_data = &(const struct clk_parent_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) .hw = &disp_cc_mdss_dp_link_clk_src.clkr.hw
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) .ops = &clk_regmap_div_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) static struct clk_branch disp_cc_mdss_byte0_intf_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) .halt_reg = 0x202c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) .halt_check = BRANCH_HALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) .enable_reg = 0x202c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) .name = "disp_cc_mdss_byte0_intf_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) .parent_data = &(const struct clk_parent_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) .hw = &disp_cc_mdss_byte0_div_clk_src.clkr.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) static struct clk_branch disp_cc_mdss_dp_aux_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) .halt_reg = 0x2054,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) .halt_check = BRANCH_HALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) .enable_reg = 0x2054,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) .name = "disp_cc_mdss_dp_aux_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) .parent_data = &(const struct clk_parent_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) .hw = &disp_cc_mdss_dp_aux_clk_src.clkr.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) static struct clk_branch disp_cc_mdss_dp_crypto_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) .halt_reg = 0x2048,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) .halt_check = BRANCH_HALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) .enable_reg = 0x2048,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) .name = "disp_cc_mdss_dp_crypto_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) .parent_data = &(const struct clk_parent_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) .hw = &disp_cc_mdss_dp_crypto_clk_src.clkr.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) static struct clk_branch disp_cc_mdss_dp_link_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) .halt_reg = 0x2040,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) .halt_check = BRANCH_HALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) .enable_reg = 0x2040,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) .name = "disp_cc_mdss_dp_link_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) .parent_data = &(const struct clk_parent_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) .hw = &disp_cc_mdss_dp_link_clk_src.clkr.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) static struct clk_branch disp_cc_mdss_dp_link_intf_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) .halt_reg = 0x2044,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) .halt_check = BRANCH_HALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) .enable_reg = 0x2044,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) .name = "disp_cc_mdss_dp_link_intf_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) .parent_data = &(const struct clk_parent_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) .hw = &disp_cc_mdss_dp_link_div_clk_src.clkr.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) static struct clk_branch disp_cc_mdss_dp_pixel_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) .halt_reg = 0x204c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) .halt_check = BRANCH_HALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) .enable_reg = 0x204c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) .name = "disp_cc_mdss_dp_pixel_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) .parent_data = &(const struct clk_parent_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) .hw = &disp_cc_mdss_dp_pixel_clk_src.clkr.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) static struct clk_branch disp_cc_mdss_esc0_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) .halt_reg = 0x2038,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) .halt_check = BRANCH_HALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) .enable_reg = 0x2038,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) .name = "disp_cc_mdss_esc0_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) .parent_data = &(const struct clk_parent_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) .hw = &disp_cc_mdss_esc0_clk_src.clkr.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) static struct clk_branch disp_cc_mdss_mdp_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) .halt_reg = 0x200c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) .halt_check = BRANCH_HALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) .enable_reg = 0x200c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) .name = "disp_cc_mdss_mdp_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) .parent_data = &(const struct clk_parent_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) .hw = &disp_cc_mdss_mdp_clk_src.clkr.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) static struct clk_branch disp_cc_mdss_mdp_lut_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) .halt_reg = 0x201c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) .halt_check = BRANCH_VOTED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) .enable_reg = 0x201c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) .name = "disp_cc_mdss_mdp_lut_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) .parent_data = &(const struct clk_parent_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) .hw = &disp_cc_mdss_mdp_clk_src.clkr.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) static struct clk_branch disp_cc_mdss_non_gdsc_ahb_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) .halt_reg = 0x4004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) .halt_check = BRANCH_VOTED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) .enable_reg = 0x4004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) .name = "disp_cc_mdss_non_gdsc_ahb_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) .parent_data = &(const struct clk_parent_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) .hw = &disp_cc_mdss_ahb_clk_src.clkr.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) static struct clk_branch disp_cc_mdss_pclk0_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) .halt_reg = 0x2004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) .halt_check = BRANCH_HALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) .enable_reg = 0x2004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) .name = "disp_cc_mdss_pclk0_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) .parent_data = &(const struct clk_parent_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) .hw = &disp_cc_mdss_pclk0_clk_src.clkr.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) static struct clk_branch disp_cc_mdss_rot_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) .halt_reg = 0x2014,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) .halt_check = BRANCH_HALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) .enable_reg = 0x2014,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) .name = "disp_cc_mdss_rot_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) .parent_data = &(const struct clk_parent_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) .hw = &disp_cc_mdss_rot_clk_src.clkr.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) static struct clk_branch disp_cc_mdss_rscc_vsync_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) .halt_reg = 0x4008,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) .halt_check = BRANCH_HALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) .enable_reg = 0x4008,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) .name = "disp_cc_mdss_rscc_vsync_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) .parent_data = &(const struct clk_parent_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) .hw = &disp_cc_mdss_vsync_clk_src.clkr.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) static struct clk_branch disp_cc_mdss_vsync_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) .halt_reg = 0x2024,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) .halt_check = BRANCH_HALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) .enable_reg = 0x2024,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) .name = "disp_cc_mdss_vsync_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) .parent_data = &(const struct clk_parent_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) .hw = &disp_cc_mdss_vsync_clk_src.clkr.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) static struct gdsc mdss_gdsc = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) .gdscr = 0x3000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) .pd = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) .name = "mdss_gdsc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) .pwrsts = PWRSTS_OFF_ON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) .flags = HW_CTRL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) static struct gdsc *disp_cc_sc7180_gdscs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) [MDSS_GDSC] = &mdss_gdsc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) static struct clk_regmap *disp_cc_sc7180_clocks[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) [DISP_CC_MDSS_AHB_CLK] = &disp_cc_mdss_ahb_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) [DISP_CC_MDSS_AHB_CLK_SRC] = &disp_cc_mdss_ahb_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) [DISP_CC_MDSS_BYTE0_CLK] = &disp_cc_mdss_byte0_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) [DISP_CC_MDSS_BYTE0_CLK_SRC] = &disp_cc_mdss_byte0_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) [DISP_CC_MDSS_BYTE0_DIV_CLK_SRC] = &disp_cc_mdss_byte0_div_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) [DISP_CC_MDSS_BYTE0_INTF_CLK] = &disp_cc_mdss_byte0_intf_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) [DISP_CC_MDSS_DP_AUX_CLK] = &disp_cc_mdss_dp_aux_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) [DISP_CC_MDSS_DP_AUX_CLK_SRC] = &disp_cc_mdss_dp_aux_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) [DISP_CC_MDSS_DP_CRYPTO_CLK] = &disp_cc_mdss_dp_crypto_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) [DISP_CC_MDSS_DP_CRYPTO_CLK_SRC] = &disp_cc_mdss_dp_crypto_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) [DISP_CC_MDSS_DP_LINK_CLK] = &disp_cc_mdss_dp_link_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) [DISP_CC_MDSS_DP_LINK_CLK_SRC] = &disp_cc_mdss_dp_link_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) [DISP_CC_MDSS_DP_LINK_DIV_CLK_SRC] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) &disp_cc_mdss_dp_link_div_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) [DISP_CC_MDSS_DP_LINK_INTF_CLK] = &disp_cc_mdss_dp_link_intf_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) [DISP_CC_MDSS_DP_PIXEL_CLK] = &disp_cc_mdss_dp_pixel_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) [DISP_CC_MDSS_DP_PIXEL_CLK_SRC] = &disp_cc_mdss_dp_pixel_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) [DISP_CC_MDSS_ESC0_CLK] = &disp_cc_mdss_esc0_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) [DISP_CC_MDSS_ESC0_CLK_SRC] = &disp_cc_mdss_esc0_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) [DISP_CC_MDSS_MDP_CLK] = &disp_cc_mdss_mdp_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) [DISP_CC_MDSS_MDP_CLK_SRC] = &disp_cc_mdss_mdp_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) [DISP_CC_MDSS_MDP_LUT_CLK] = &disp_cc_mdss_mdp_lut_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) [DISP_CC_MDSS_NON_GDSC_AHB_CLK] = &disp_cc_mdss_non_gdsc_ahb_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) [DISP_CC_MDSS_PCLK0_CLK] = &disp_cc_mdss_pclk0_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) [DISP_CC_MDSS_PCLK0_CLK_SRC] = &disp_cc_mdss_pclk0_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) [DISP_CC_MDSS_ROT_CLK] = &disp_cc_mdss_rot_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) [DISP_CC_MDSS_ROT_CLK_SRC] = &disp_cc_mdss_rot_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) [DISP_CC_MDSS_RSCC_VSYNC_CLK] = &disp_cc_mdss_rscc_vsync_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) [DISP_CC_MDSS_VSYNC_CLK] = &disp_cc_mdss_vsync_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) [DISP_CC_MDSS_VSYNC_CLK_SRC] = &disp_cc_mdss_vsync_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) [DISP_CC_PLL0] = &disp_cc_pll0.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) [DISP_CC_PLL0_OUT_EVEN] = &disp_cc_pll0_out_even.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) static const struct regmap_config disp_cc_sc7180_regmap_config = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) .reg_bits = 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) .reg_stride = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) .val_bits = 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) .max_register = 0x10000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) .fast_io = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) static const struct qcom_cc_desc disp_cc_sc7180_desc = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) .config = &disp_cc_sc7180_regmap_config,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) .clks = disp_cc_sc7180_clocks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) .num_clks = ARRAY_SIZE(disp_cc_sc7180_clocks),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) .gdscs = disp_cc_sc7180_gdscs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) .num_gdscs = ARRAY_SIZE(disp_cc_sc7180_gdscs),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) static const struct of_device_id disp_cc_sc7180_match_table[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) { .compatible = "qcom,sc7180-dispcc" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) MODULE_DEVICE_TABLE(of, disp_cc_sc7180_match_table);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) static int disp_cc_sc7180_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) struct regmap *regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) struct alpha_pll_config disp_cc_pll_config = {};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) regmap = qcom_cc_map(pdev, &disp_cc_sc7180_desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) if (IS_ERR(regmap))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) return PTR_ERR(regmap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) /* 1380MHz configuration */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) disp_cc_pll_config.l = 0x47;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) disp_cc_pll_config.alpha = 0xe000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) disp_cc_pll_config.user_ctl_val = 0x00000001;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) disp_cc_pll_config.user_ctl_hi_val = 0x00004805;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) clk_fabia_pll_configure(&disp_cc_pll0, regmap, &disp_cc_pll_config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) return qcom_cc_really_probe(pdev, &disp_cc_sc7180_desc, regmap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) static struct platform_driver disp_cc_sc7180_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) .probe = disp_cc_sc7180_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) .name = "sc7180-dispcc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) .of_match_table = disp_cc_sc7180_match_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) static int __init disp_cc_sc7180_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) return platform_driver_register(&disp_cc_sc7180_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) subsys_initcall(disp_cc_sc7180_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) static void __exit disp_cc_sc7180_exit(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) platform_driver_unregister(&disp_cc_sc7180_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) module_exit(disp_cc_sc7180_exit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) MODULE_DESCRIPTION("QTI DISP_CC SC7180 Driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) MODULE_LICENSE("GPL v2");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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