Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) /* SPDX-License-Identifier: GPL-2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) /* Copyright (c) 2014, The Linux Foundation. All rights reserved. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4) #ifndef __QCOM_CLK_COMMON_H__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5) #define __QCOM_CLK_COMMON_H__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7) struct platform_device;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8) struct regmap_config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9) struct clk_regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) struct qcom_reset_map;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) struct regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) struct freq_tbl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) struct clk_hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define PLL_LOCK_COUNT_SHIFT	8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define PLL_LOCK_COUNT_MASK	0x3f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define PLL_BIAS_COUNT_SHIFT	14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define PLL_BIAS_COUNT_MASK	0x3f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define PLL_VOTE_FSM_ENA	BIT(20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define PLL_VOTE_FSM_RESET	BIT(21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) struct qcom_cc_desc {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) 	const struct regmap_config *config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) 	struct clk_regmap **clks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) 	size_t num_clks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) 	const struct qcom_reset_map *resets;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) 	size_t num_resets;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) 	struct gdsc **gdscs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) 	size_t num_gdscs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) 	struct clk_hw **clk_hws;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) 	size_t num_clk_hws;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)  * struct parent_map - map table for source select configuration values
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)  * @src: source
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37)  * @cfg: configuration value
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) struct parent_map {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) 	u8 src;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) 	u8 cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) extern const struct freq_tbl *qcom_find_freq(const struct freq_tbl *f,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) 					     unsigned long rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) extern const struct freq_tbl *qcom_find_freq_floor(const struct freq_tbl *f,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) 						   unsigned long rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) extern void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) qcom_pll_set_fsm_mode(struct regmap *m, u32 reg, u8 bias_count, u8 lock_count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) extern int qcom_find_src_index(struct clk_hw *hw, const struct parent_map *map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) 			       u8 src);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) extern int qcom_find_cfg_index(struct clk_hw *hw, const struct parent_map *map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) 			       u8 cfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) extern int qcom_cc_register_board_clk(struct device *dev, const char *path,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) 				      const char *name, unsigned long rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) extern int qcom_cc_register_sleep_clk(struct device *dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) extern struct regmap *qcom_cc_map(struct platform_device *pdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) 				  const struct qcom_cc_desc *desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) extern int qcom_cc_really_probe(struct platform_device *pdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) 				const struct qcom_cc_desc *desc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) 				struct regmap *regmap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) extern int qcom_cc_probe(struct platform_device *pdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) 			 const struct qcom_cc_desc *desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) extern int qcom_cc_probe_by_index(struct platform_device *pdev, int index,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) 				  const struct qcom_cc_desc *desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #endif