Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * Copyright (c) 2013-2014, The Linux Foundation. All rights reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6) #include <linux/export.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8) #include <linux/regmap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) #include <linux/clk-provider.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #include <linux/reset-controller.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #include "common.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #include "clk-rcg.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #include "clk-regmap.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #include "reset.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #include "gdsc.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) struct qcom_cc {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) 	struct qcom_reset_controller reset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) 	struct clk_regmap **rclks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) 	size_t num_rclks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) const
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) struct freq_tbl *qcom_find_freq(const struct freq_tbl *f, unsigned long rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) 	if (!f)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) 		return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) 	if (!f->freq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) 		return f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) 	for (; f->freq; f++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) 		if (rate <= f->freq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) 			return f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) 	/* Default to our fastest rate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) 	return f - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) EXPORT_SYMBOL_GPL(qcom_find_freq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) const struct freq_tbl *qcom_find_freq_floor(const struct freq_tbl *f,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) 					    unsigned long rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) 	const struct freq_tbl *best = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) 	for ( ; f->freq; f++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) 		if (rate >= f->freq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) 			best = f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) 		else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) 			break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) 	return best;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) EXPORT_SYMBOL_GPL(qcom_find_freq_floor);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) int qcom_find_src_index(struct clk_hw *hw, const struct parent_map *map, u8 src)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 	int i, num_parents = clk_hw_get_num_parents(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 	for (i = 0; i < num_parents; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 		if (src == map[i].src)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 			return i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 	return -ENOENT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) EXPORT_SYMBOL_GPL(qcom_find_src_index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) int qcom_find_cfg_index(struct clk_hw *hw, const struct parent_map *map, u8 cfg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 	int i, num_parents = clk_hw_get_num_parents(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 	for (i = 0; i < num_parents; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 		if (cfg == map[i].cfg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 			return i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 	return -ENOENT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) EXPORT_SYMBOL_GPL(qcom_find_cfg_index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) struct regmap *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) qcom_cc_map(struct platform_device *pdev, const struct qcom_cc_desc *desc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 	void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 	struct resource *res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 	struct device *dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 	base = devm_ioremap_resource(dev, res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 	if (IS_ERR(base))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 		return ERR_CAST(base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 	return devm_regmap_init_mmio(dev, base, desc->config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) EXPORT_SYMBOL_GPL(qcom_cc_map);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) qcom_pll_set_fsm_mode(struct regmap *map, u32 reg, u8 bias_count, u8 lock_count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 	u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 	u32 mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 	/* De-assert reset to FSM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 	regmap_update_bits(map, reg, PLL_VOTE_FSM_RESET, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 	/* Program bias count and lock count */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 	val = bias_count << PLL_BIAS_COUNT_SHIFT |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 		lock_count << PLL_LOCK_COUNT_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 	mask = PLL_BIAS_COUNT_MASK << PLL_BIAS_COUNT_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 	mask |= PLL_LOCK_COUNT_MASK << PLL_LOCK_COUNT_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 	regmap_update_bits(map, reg, mask, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 	/* Enable PLL FSM voting */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 	regmap_update_bits(map, reg, PLL_VOTE_FSM_ENA, PLL_VOTE_FSM_ENA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) EXPORT_SYMBOL_GPL(qcom_pll_set_fsm_mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) static void qcom_cc_gdsc_unregister(void *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 	gdsc_unregister(data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127)  * Backwards compatibility with old DTs. Register a pass-through factor 1/1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128)  * clock to translate 'path' clk into 'name' clk and register the 'path'
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129)  * clk as a fixed rate clock if it isn't present.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) static int _qcom_cc_register_board_clk(struct device *dev, const char *path,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 				       const char *name, unsigned long rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 				       bool add_factor)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 	struct device_node *node = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 	struct device_node *clocks_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 	struct clk_fixed_factor *factor;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 	struct clk_fixed_rate *fixed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 	struct clk_init_data init_data = { };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 	clocks_node = of_find_node_by_path("/clocks");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 	if (clocks_node) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 		node = of_get_child_by_name(clocks_node, path);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 		of_node_put(clocks_node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 	if (!node) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 		fixed = devm_kzalloc(dev, sizeof(*fixed), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 		if (!fixed)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 			return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 		fixed->fixed_rate = rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 		fixed->hw.init = &init_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 		init_data.name = path;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 		init_data.ops = &clk_fixed_rate_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 		ret = devm_clk_hw_register(dev, &fixed->hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 		if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 			return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 	of_node_put(node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 	if (add_factor) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 		factor = devm_kzalloc(dev, sizeof(*factor), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 		if (!factor)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 			return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 		factor->mult = factor->div = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 		factor->hw.init = &init_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 		init_data.name = name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 		init_data.parent_names = &path;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 		init_data.num_parents = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 		init_data.flags = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 		init_data.ops = &clk_fixed_factor_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 		ret = devm_clk_hw_register(dev, &factor->hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 		if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 			return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) int qcom_cc_register_board_clk(struct device *dev, const char *path,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 			       const char *name, unsigned long rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 	bool add_factor = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 	 * TODO: The RPM clock driver currently does not support the xo clock.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 	 * When xo is added to the RPM clock driver, we should change this
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 	 * function to skip registration of xo factor clocks.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 	return _qcom_cc_register_board_clk(dev, path, name, rate, add_factor);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) EXPORT_SYMBOL_GPL(qcom_cc_register_board_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) int qcom_cc_register_sleep_clk(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 	return _qcom_cc_register_board_clk(dev, "sleep_clk", "sleep_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 					   32768, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) EXPORT_SYMBOL_GPL(qcom_cc_register_sleep_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) /* Drop 'protected-clocks' from the list of clocks to register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) static void qcom_cc_drop_protected(struct device *dev, struct qcom_cc *cc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 	struct device_node *np = dev->of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 	struct property *prop;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 	const __be32 *p;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 	u32 i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 	of_property_for_each_u32(np, "protected-clocks", prop, p, i) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 		if (i >= cc->num_rclks)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 			continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 		cc->rclks[i] = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) static struct clk_hw *qcom_cc_clk_hw_get(struct of_phandle_args *clkspec,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 					 void *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 	struct qcom_cc *cc = data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 	unsigned int idx = clkspec->args[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 	if (idx >= cc->num_rclks) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 		pr_err("%s: invalid index %u\n", __func__, idx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 		return ERR_PTR(-EINVAL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 	return cc->rclks[idx] ? &cc->rclks[idx]->hw : NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) int qcom_cc_really_probe(struct platform_device *pdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 			 const struct qcom_cc_desc *desc, struct regmap *regmap)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 	int i, ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 	struct device *dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 	struct qcom_reset_controller *reset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 	struct qcom_cc *cc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 	struct gdsc_desc *scd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 	size_t num_clks = desc->num_clks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 	struct clk_regmap **rclks = desc->clks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 	size_t num_clk_hws = desc->num_clk_hws;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 	struct clk_hw **clk_hws = desc->clk_hws;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 	cc = devm_kzalloc(dev, sizeof(*cc), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) 	if (!cc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 		return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) 	reset = &cc->reset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) 	reset->rcdev.of_node = dev->of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) 	reset->rcdev.ops = &qcom_reset_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) 	reset->rcdev.owner = dev->driver->owner;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) 	reset->rcdev.nr_resets = desc->num_resets;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) 	reset->regmap = regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) 	reset->reset_map = desc->resets;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) 	ret = devm_reset_controller_register(dev, &reset->rcdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) 	if (desc->gdscs && desc->num_gdscs) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) 		scd = devm_kzalloc(dev, sizeof(*scd), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) 		if (!scd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) 			return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) 		scd->dev = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) 		scd->scs = desc->gdscs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) 		scd->num = desc->num_gdscs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) 		ret = gdsc_register(scd, &reset->rcdev, regmap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) 		if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) 			return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) 		ret = devm_add_action_or_reset(dev, qcom_cc_gdsc_unregister,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) 					       scd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) 		if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) 			return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) 	cc->rclks = rclks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) 	cc->num_rclks = num_clks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) 	qcom_cc_drop_protected(dev, cc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) 	for (i = 0; i < num_clk_hws; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) 		ret = devm_clk_hw_register(dev, clk_hws[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) 		if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) 			return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) 	for (i = 0; i < num_clks; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) 		if (!rclks[i])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) 			continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) 		ret = devm_clk_register_regmap(dev, rclks[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) 		if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) 			return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) 	ret = devm_of_clk_add_hw_provider(dev, qcom_cc_clk_hw_get, cc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) EXPORT_SYMBOL_GPL(qcom_cc_really_probe);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) int qcom_cc_probe(struct platform_device *pdev, const struct qcom_cc_desc *desc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) 	struct regmap *regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) 	regmap = qcom_cc_map(pdev, desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) 	if (IS_ERR(regmap))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) 		return PTR_ERR(regmap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) 	return qcom_cc_really_probe(pdev, desc, regmap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) EXPORT_SYMBOL_GPL(qcom_cc_probe);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) int qcom_cc_probe_by_index(struct platform_device *pdev, int index,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) 			   const struct qcom_cc_desc *desc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) 	struct regmap *regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) 	struct resource *res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) 	void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) 	res = platform_get_resource(pdev, IORESOURCE_MEM, index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) 	base = devm_ioremap_resource(&pdev->dev, res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) 	if (IS_ERR(base))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) 		return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) 	regmap = devm_regmap_init_mmio(&pdev->dev, base, desc->config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) 	if (IS_ERR(regmap))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) 		return PTR_ERR(regmap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) 	return qcom_cc_really_probe(pdev, desc, regmap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) EXPORT_SYMBOL_GPL(qcom_cc_probe_by_index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) MODULE_LICENSE("GPL v2");