^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (c) 2016, Linaro Limited
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Copyright (c) 2014, The Linux Foundation. All rights reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include <linux/clk-provider.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/export.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/mutex.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/of_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/soc/qcom/smd-rpm.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <dt-bindings/clock/qcom,rpmcc.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <dt-bindings/mfd/qcom-rpm.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define QCOM_RPM_KEY_SOFTWARE_ENABLE 0x6e657773
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define QCOM_RPM_KEY_PIN_CTRL_CLK_BUFFER_ENABLE_KEY 0x62636370
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define QCOM_RPM_SMD_KEY_RATE 0x007a484b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define QCOM_RPM_SMD_KEY_ENABLE 0x62616e45
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define QCOM_RPM_SMD_KEY_STATE 0x54415453
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define QCOM_RPM_SCALING_ENABLE_ID 0x2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define __DEFINE_CLK_SMD_RPM(_platform, _name, _active, type, r_id, stat_id, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) key) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) static struct clk_smd_rpm _platform##_##_active; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) static struct clk_smd_rpm _platform##_##_name = { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) .rpm_res_type = (type), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) .rpm_clk_id = (r_id), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) .rpm_status_id = (stat_id), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) .rpm_key = (key), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) .peer = &_platform##_##_active, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) .rate = INT_MAX, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) .hw.init = &(struct clk_init_data){ \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) .ops = &clk_smd_rpm_ops, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) .name = #_name, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) .parent_names = (const char *[]){ "xo_board" }, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) .num_parents = 1, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) }, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) }; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) static struct clk_smd_rpm _platform##_##_active = { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) .rpm_res_type = (type), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) .rpm_clk_id = (r_id), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) .rpm_status_id = (stat_id), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) .active_only = true, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) .rpm_key = (key), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) .peer = &_platform##_##_name, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) .rate = INT_MAX, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) .hw.init = &(struct clk_init_data){ \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) .ops = &clk_smd_rpm_ops, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) .name = #_active, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) .parent_names = (const char *[]){ "xo_board" }, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) .num_parents = 1, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) }, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define __DEFINE_CLK_SMD_RPM_BRANCH(_platform, _name, _active, type, r_id, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) stat_id, r, key) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) static struct clk_smd_rpm _platform##_##_active; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) static struct clk_smd_rpm _platform##_##_name = { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) .rpm_res_type = (type), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) .rpm_clk_id = (r_id), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) .rpm_status_id = (stat_id), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) .rpm_key = (key), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) .branch = true, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) .peer = &_platform##_##_active, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) .rate = (r), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) .hw.init = &(struct clk_init_data){ \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) .ops = &clk_smd_rpm_branch_ops, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) .name = #_name, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) .parent_names = (const char *[]){ "xo_board" }, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) .num_parents = 1, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) }, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) }; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) static struct clk_smd_rpm _platform##_##_active = { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) .rpm_res_type = (type), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) .rpm_clk_id = (r_id), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) .rpm_status_id = (stat_id), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) .active_only = true, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) .rpm_key = (key), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) .branch = true, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) .peer = &_platform##_##_name, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) .rate = (r), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) .hw.init = &(struct clk_init_data){ \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) .ops = &clk_smd_rpm_branch_ops, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) .name = #_active, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) .parent_names = (const char *[]){ "xo_board" }, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) .num_parents = 1, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) }, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define DEFINE_CLK_SMD_RPM(_platform, _name, _active, type, r_id) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) __DEFINE_CLK_SMD_RPM(_platform, _name, _active, type, r_id, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) 0, QCOM_RPM_SMD_KEY_RATE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define DEFINE_CLK_SMD_RPM_BRANCH(_platform, _name, _active, type, r_id, r) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) __DEFINE_CLK_SMD_RPM_BRANCH(_platform, _name, _active, type, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) r_id, 0, r, QCOM_RPM_SMD_KEY_ENABLE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define DEFINE_CLK_SMD_RPM_QDSS(_platform, _name, _active, type, r_id) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) __DEFINE_CLK_SMD_RPM(_platform, _name, _active, type, r_id, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 0, QCOM_RPM_SMD_KEY_STATE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define DEFINE_CLK_SMD_RPM_XO_BUFFER(_platform, _name, _active, r_id) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) __DEFINE_CLK_SMD_RPM_BRANCH(_platform, _name, _active, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) QCOM_SMD_RPM_CLK_BUF_A, r_id, 0, 1000, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) QCOM_RPM_KEY_SOFTWARE_ENABLE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(_platform, _name, _active, r_id) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) __DEFINE_CLK_SMD_RPM_BRANCH(_platform, _name, _active, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) QCOM_SMD_RPM_CLK_BUF_A, r_id, 0, 1000, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) QCOM_RPM_KEY_PIN_CTRL_CLK_BUFFER_ENABLE_KEY)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define to_clk_smd_rpm(_hw) container_of(_hw, struct clk_smd_rpm, hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) struct clk_smd_rpm {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) const int rpm_res_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) const int rpm_key;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) const int rpm_clk_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) const int rpm_status_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) const bool active_only;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) bool enabled;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) bool branch;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) struct clk_smd_rpm *peer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) struct clk_hw hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) unsigned long rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) struct qcom_smd_rpm *rpm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) struct clk_smd_rpm_req {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) __le32 key;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) __le32 nbytes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) __le32 value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) struct rpm_cc {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) struct qcom_rpm *rpm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) struct clk_smd_rpm **clks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) size_t num_clks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) struct rpm_smd_clk_desc {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) struct clk_smd_rpm **clks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) size_t num_clks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) static DEFINE_MUTEX(rpm_smd_clk_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) static int clk_smd_rpm_handoff(struct clk_smd_rpm *r)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) struct clk_smd_rpm_req req = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) .key = cpu_to_le32(r->rpm_key),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) .nbytes = cpu_to_le32(sizeof(u32)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) .value = cpu_to_le32(r->branch ? 1 : INT_MAX),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) ret = qcom_rpm_smd_write(r->rpm, QCOM_SMD_RPM_ACTIVE_STATE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) r->rpm_res_type, r->rpm_clk_id, &req,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) sizeof(req));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) ret = qcom_rpm_smd_write(r->rpm, QCOM_SMD_RPM_SLEEP_STATE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) r->rpm_res_type, r->rpm_clk_id, &req,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) sizeof(req));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) static int clk_smd_rpm_set_rate_active(struct clk_smd_rpm *r,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) unsigned long rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) struct clk_smd_rpm_req req = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) .key = cpu_to_le32(r->rpm_key),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) .nbytes = cpu_to_le32(sizeof(u32)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) .value = cpu_to_le32(DIV_ROUND_UP(rate, 1000)), /* to kHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) return qcom_rpm_smd_write(r->rpm, QCOM_SMD_RPM_ACTIVE_STATE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) r->rpm_res_type, r->rpm_clk_id, &req,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) sizeof(req));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) static int clk_smd_rpm_set_rate_sleep(struct clk_smd_rpm *r,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) unsigned long rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) struct clk_smd_rpm_req req = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) .key = cpu_to_le32(r->rpm_key),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) .nbytes = cpu_to_le32(sizeof(u32)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) .value = cpu_to_le32(DIV_ROUND_UP(rate, 1000)), /* to kHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) return qcom_rpm_smd_write(r->rpm, QCOM_SMD_RPM_SLEEP_STATE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) r->rpm_res_type, r->rpm_clk_id, &req,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) sizeof(req));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) static void to_active_sleep(struct clk_smd_rpm *r, unsigned long rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) unsigned long *active, unsigned long *sleep)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) *active = rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) * Active-only clocks don't care what the rate is during sleep. So,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) * they vote for zero.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) if (r->active_only)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) *sleep = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) *sleep = *active;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) static int clk_smd_rpm_prepare(struct clk_hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) struct clk_smd_rpm *r = to_clk_smd_rpm(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) struct clk_smd_rpm *peer = r->peer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) unsigned long this_rate = 0, this_sleep_rate = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) unsigned long peer_rate = 0, peer_sleep_rate = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) unsigned long active_rate, sleep_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) mutex_lock(&rpm_smd_clk_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) /* Don't send requests to the RPM if the rate has not been set. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) if (!r->rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) to_active_sleep(r, r->rate, &this_rate, &this_sleep_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) /* Take peer clock's rate into account only if it's enabled. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) if (peer->enabled)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) to_active_sleep(peer, peer->rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) &peer_rate, &peer_sleep_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) active_rate = max(this_rate, peer_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) if (r->branch)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) active_rate = !!active_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) ret = clk_smd_rpm_set_rate_active(r, active_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) sleep_rate = max(this_sleep_rate, peer_sleep_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) if (r->branch)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) sleep_rate = !!sleep_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) ret = clk_smd_rpm_set_rate_sleep(r, sleep_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) /* Undo the active set vote and restore it */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) ret = clk_smd_rpm_set_rate_active(r, peer_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) if (!ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) r->enabled = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) mutex_unlock(&rpm_smd_clk_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) static void clk_smd_rpm_unprepare(struct clk_hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) struct clk_smd_rpm *r = to_clk_smd_rpm(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) struct clk_smd_rpm *peer = r->peer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) unsigned long peer_rate = 0, peer_sleep_rate = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) unsigned long active_rate, sleep_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) mutex_lock(&rpm_smd_clk_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) if (!r->rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) /* Take peer clock's rate into account only if it's enabled. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) if (peer->enabled)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) to_active_sleep(peer, peer->rate, &peer_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) &peer_sleep_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) active_rate = r->branch ? !!peer_rate : peer_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) ret = clk_smd_rpm_set_rate_active(r, active_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) sleep_rate = r->branch ? !!peer_sleep_rate : peer_sleep_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) ret = clk_smd_rpm_set_rate_sleep(r, sleep_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) r->enabled = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) mutex_unlock(&rpm_smd_clk_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) static int clk_smd_rpm_set_rate(struct clk_hw *hw, unsigned long rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) unsigned long parent_rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) struct clk_smd_rpm *r = to_clk_smd_rpm(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) struct clk_smd_rpm *peer = r->peer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) unsigned long active_rate, sleep_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) unsigned long this_rate = 0, this_sleep_rate = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) unsigned long peer_rate = 0, peer_sleep_rate = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) mutex_lock(&rpm_smd_clk_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) if (!r->enabled)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) to_active_sleep(r, rate, &this_rate, &this_sleep_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) /* Take peer clock's rate into account only if it's enabled. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) if (peer->enabled)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) to_active_sleep(peer, peer->rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) &peer_rate, &peer_sleep_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) active_rate = max(this_rate, peer_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) ret = clk_smd_rpm_set_rate_active(r, active_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) sleep_rate = max(this_sleep_rate, peer_sleep_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) ret = clk_smd_rpm_set_rate_sleep(r, sleep_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) r->rate = rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) mutex_unlock(&rpm_smd_clk_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) static long clk_smd_rpm_round_rate(struct clk_hw *hw, unsigned long rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) unsigned long *parent_rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) * RPM handles rate rounding and we don't have a way to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) * know what the rate will be, so just return whatever
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) * rate is requested.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) return rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) static unsigned long clk_smd_rpm_recalc_rate(struct clk_hw *hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) unsigned long parent_rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) struct clk_smd_rpm *r = to_clk_smd_rpm(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) * RPM handles rate rounding and we don't have a way to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) * know what the rate will be, so just return whatever
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) * rate was set.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) return r->rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) static int clk_smd_rpm_enable_scaling(struct qcom_smd_rpm *rpm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) struct clk_smd_rpm_req req = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) .key = cpu_to_le32(QCOM_RPM_SMD_KEY_ENABLE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) .nbytes = cpu_to_le32(sizeof(u32)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) .value = cpu_to_le32(1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) ret = qcom_rpm_smd_write(rpm, QCOM_SMD_RPM_SLEEP_STATE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) QCOM_SMD_RPM_MISC_CLK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) QCOM_RPM_SCALING_ENABLE_ID, &req, sizeof(req));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) pr_err("RPM clock scaling (sleep set) not enabled!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) ret = qcom_rpm_smd_write(rpm, QCOM_SMD_RPM_ACTIVE_STATE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) QCOM_SMD_RPM_MISC_CLK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) QCOM_RPM_SCALING_ENABLE_ID, &req, sizeof(req));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) pr_err("RPM clock scaling (active set) not enabled!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) pr_debug("%s: RPM clock scaling is enabled\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) static const struct clk_ops clk_smd_rpm_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) .prepare = clk_smd_rpm_prepare,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) .unprepare = clk_smd_rpm_unprepare,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) .set_rate = clk_smd_rpm_set_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) .round_rate = clk_smd_rpm_round_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) .recalc_rate = clk_smd_rpm_recalc_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) static const struct clk_ops clk_smd_rpm_branch_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) .prepare = clk_smd_rpm_prepare,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) .unprepare = clk_smd_rpm_unprepare,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) /* msm8916 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) DEFINE_CLK_SMD_RPM(msm8916, pcnoc_clk, pcnoc_a_clk, QCOM_SMD_RPM_BUS_CLK, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) DEFINE_CLK_SMD_RPM(msm8916, snoc_clk, snoc_a_clk, QCOM_SMD_RPM_BUS_CLK, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) DEFINE_CLK_SMD_RPM(msm8916, bimc_clk, bimc_a_clk, QCOM_SMD_RPM_MEM_CLK, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) DEFINE_CLK_SMD_RPM_QDSS(msm8916, qdss_clk, qdss_a_clk, QCOM_SMD_RPM_MISC_CLK, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) DEFINE_CLK_SMD_RPM_XO_BUFFER(msm8916, bb_clk1, bb_clk1_a, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) DEFINE_CLK_SMD_RPM_XO_BUFFER(msm8916, bb_clk2, bb_clk2_a, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) DEFINE_CLK_SMD_RPM_XO_BUFFER(msm8916, rf_clk1, rf_clk1_a, 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) DEFINE_CLK_SMD_RPM_XO_BUFFER(msm8916, rf_clk2, rf_clk2_a, 5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(msm8916, bb_clk1_pin, bb_clk1_a_pin, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(msm8916, bb_clk2_pin, bb_clk2_a_pin, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(msm8916, rf_clk1_pin, rf_clk1_a_pin, 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(msm8916, rf_clk2_pin, rf_clk2_a_pin, 5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) static struct clk_smd_rpm *msm8916_clks[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) [RPM_SMD_PCNOC_CLK] = &msm8916_pcnoc_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) [RPM_SMD_PCNOC_A_CLK] = &msm8916_pcnoc_a_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) [RPM_SMD_SNOC_CLK] = &msm8916_snoc_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) [RPM_SMD_SNOC_A_CLK] = &msm8916_snoc_a_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) [RPM_SMD_BIMC_CLK] = &msm8916_bimc_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) [RPM_SMD_BIMC_A_CLK] = &msm8916_bimc_a_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) [RPM_SMD_QDSS_CLK] = &msm8916_qdss_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) [RPM_SMD_QDSS_A_CLK] = &msm8916_qdss_a_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) [RPM_SMD_BB_CLK1] = &msm8916_bb_clk1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) [RPM_SMD_BB_CLK1_A] = &msm8916_bb_clk1_a,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) [RPM_SMD_BB_CLK2] = &msm8916_bb_clk2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) [RPM_SMD_BB_CLK2_A] = &msm8916_bb_clk2_a,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) [RPM_SMD_RF_CLK1] = &msm8916_rf_clk1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) [RPM_SMD_RF_CLK1_A] = &msm8916_rf_clk1_a,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) [RPM_SMD_RF_CLK2] = &msm8916_rf_clk2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) [RPM_SMD_RF_CLK2_A] = &msm8916_rf_clk2_a,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) [RPM_SMD_BB_CLK1_PIN] = &msm8916_bb_clk1_pin,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) [RPM_SMD_BB_CLK1_A_PIN] = &msm8916_bb_clk1_a_pin,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) [RPM_SMD_BB_CLK2_PIN] = &msm8916_bb_clk2_pin,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) [RPM_SMD_BB_CLK2_A_PIN] = &msm8916_bb_clk2_a_pin,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) [RPM_SMD_RF_CLK1_PIN] = &msm8916_rf_clk1_pin,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) [RPM_SMD_RF_CLK1_A_PIN] = &msm8916_rf_clk1_a_pin,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) [RPM_SMD_RF_CLK2_PIN] = &msm8916_rf_clk2_pin,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) [RPM_SMD_RF_CLK2_A_PIN] = &msm8916_rf_clk2_a_pin,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) static const struct rpm_smd_clk_desc rpm_clk_msm8916 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) .clks = msm8916_clks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) .num_clks = ARRAY_SIZE(msm8916_clks),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) /* msm8936 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) DEFINE_CLK_SMD_RPM(msm8936, pcnoc_clk, pcnoc_a_clk, QCOM_SMD_RPM_BUS_CLK, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) DEFINE_CLK_SMD_RPM(msm8936, snoc_clk, snoc_a_clk, QCOM_SMD_RPM_BUS_CLK, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) DEFINE_CLK_SMD_RPM(msm8936, bimc_clk, bimc_a_clk, QCOM_SMD_RPM_MEM_CLK, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) DEFINE_CLK_SMD_RPM(msm8936, sysmmnoc_clk, sysmmnoc_a_clk, QCOM_SMD_RPM_BUS_CLK, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) DEFINE_CLK_SMD_RPM_QDSS(msm8936, qdss_clk, qdss_a_clk, QCOM_SMD_RPM_MISC_CLK, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) DEFINE_CLK_SMD_RPM_XO_BUFFER(msm8936, bb_clk1, bb_clk1_a, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) DEFINE_CLK_SMD_RPM_XO_BUFFER(msm8936, bb_clk2, bb_clk2_a, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) DEFINE_CLK_SMD_RPM_XO_BUFFER(msm8936, rf_clk1, rf_clk1_a, 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) DEFINE_CLK_SMD_RPM_XO_BUFFER(msm8936, rf_clk2, rf_clk2_a, 5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(msm8936, bb_clk1_pin, bb_clk1_a_pin, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(msm8936, bb_clk2_pin, bb_clk2_a_pin, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(msm8936, rf_clk1_pin, rf_clk1_a_pin, 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(msm8936, rf_clk2_pin, rf_clk2_a_pin, 5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) static struct clk_smd_rpm *msm8936_clks[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) [RPM_SMD_PCNOC_CLK] = &msm8936_pcnoc_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) [RPM_SMD_PCNOC_A_CLK] = &msm8936_pcnoc_a_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) [RPM_SMD_SNOC_CLK] = &msm8936_snoc_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) [RPM_SMD_SNOC_A_CLK] = &msm8936_snoc_a_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) [RPM_SMD_BIMC_CLK] = &msm8936_bimc_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) [RPM_SMD_BIMC_A_CLK] = &msm8936_bimc_a_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) [RPM_SMD_SYSMMNOC_CLK] = &msm8936_sysmmnoc_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) [RPM_SMD_SYSMMNOC_A_CLK] = &msm8936_sysmmnoc_a_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) [RPM_SMD_QDSS_CLK] = &msm8936_qdss_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) [RPM_SMD_QDSS_A_CLK] = &msm8936_qdss_a_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) [RPM_SMD_BB_CLK1] = &msm8936_bb_clk1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) [RPM_SMD_BB_CLK1_A] = &msm8936_bb_clk1_a,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) [RPM_SMD_BB_CLK2] = &msm8936_bb_clk2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) [RPM_SMD_BB_CLK2_A] = &msm8936_bb_clk2_a,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) [RPM_SMD_RF_CLK1] = &msm8936_rf_clk1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) [RPM_SMD_RF_CLK1_A] = &msm8936_rf_clk1_a,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) [RPM_SMD_RF_CLK2] = &msm8936_rf_clk2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) [RPM_SMD_RF_CLK2_A] = &msm8936_rf_clk2_a,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) [RPM_SMD_BB_CLK1_PIN] = &msm8936_bb_clk1_pin,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) [RPM_SMD_BB_CLK1_A_PIN] = &msm8936_bb_clk1_a_pin,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) [RPM_SMD_BB_CLK2_PIN] = &msm8936_bb_clk2_pin,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) [RPM_SMD_BB_CLK2_A_PIN] = &msm8936_bb_clk2_a_pin,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) [RPM_SMD_RF_CLK1_PIN] = &msm8936_rf_clk1_pin,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) [RPM_SMD_RF_CLK1_A_PIN] = &msm8936_rf_clk1_a_pin,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) [RPM_SMD_RF_CLK2_PIN] = &msm8936_rf_clk2_pin,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) [RPM_SMD_RF_CLK2_A_PIN] = &msm8936_rf_clk2_a_pin,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) static const struct rpm_smd_clk_desc rpm_clk_msm8936 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) .clks = msm8936_clks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) .num_clks = ARRAY_SIZE(msm8936_clks),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) /* msm8974 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) DEFINE_CLK_SMD_RPM(msm8974, pnoc_clk, pnoc_a_clk, QCOM_SMD_RPM_BUS_CLK, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) DEFINE_CLK_SMD_RPM(msm8974, snoc_clk, snoc_a_clk, QCOM_SMD_RPM_BUS_CLK, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) DEFINE_CLK_SMD_RPM(msm8974, cnoc_clk, cnoc_a_clk, QCOM_SMD_RPM_BUS_CLK, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) DEFINE_CLK_SMD_RPM(msm8974, mmssnoc_ahb_clk, mmssnoc_ahb_a_clk, QCOM_SMD_RPM_BUS_CLK, 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) DEFINE_CLK_SMD_RPM(msm8974, bimc_clk, bimc_a_clk, QCOM_SMD_RPM_MEM_CLK, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) DEFINE_CLK_SMD_RPM(msm8974, gfx3d_clk_src, gfx3d_a_clk_src, QCOM_SMD_RPM_MEM_CLK, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) DEFINE_CLK_SMD_RPM(msm8974, ocmemgx_clk, ocmemgx_a_clk, QCOM_SMD_RPM_MEM_CLK, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) DEFINE_CLK_SMD_RPM_QDSS(msm8974, qdss_clk, qdss_a_clk, QCOM_SMD_RPM_MISC_CLK, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) DEFINE_CLK_SMD_RPM_XO_BUFFER(msm8974, cxo_d0, cxo_d0_a, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) DEFINE_CLK_SMD_RPM_XO_BUFFER(msm8974, cxo_d1, cxo_d1_a, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) DEFINE_CLK_SMD_RPM_XO_BUFFER(msm8974, cxo_a0, cxo_a0_a, 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) DEFINE_CLK_SMD_RPM_XO_BUFFER(msm8974, cxo_a1, cxo_a1_a, 5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) DEFINE_CLK_SMD_RPM_XO_BUFFER(msm8974, cxo_a2, cxo_a2_a, 6);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) DEFINE_CLK_SMD_RPM_XO_BUFFER(msm8974, diff_clk, diff_a_clk, 7);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) DEFINE_CLK_SMD_RPM_XO_BUFFER(msm8974, div_clk1, div_a_clk1, 11);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) DEFINE_CLK_SMD_RPM_XO_BUFFER(msm8974, div_clk2, div_a_clk2, 12);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(msm8974, cxo_d0_pin, cxo_d0_a_pin, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(msm8974, cxo_d1_pin, cxo_d1_a_pin, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(msm8974, cxo_a0_pin, cxo_a0_a_pin, 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(msm8974, cxo_a1_pin, cxo_a1_a_pin, 5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(msm8974, cxo_a2_pin, cxo_a2_a_pin, 6);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) static struct clk_smd_rpm *msm8974_clks[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) [RPM_SMD_PNOC_CLK] = &msm8974_pnoc_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) [RPM_SMD_PNOC_A_CLK] = &msm8974_pnoc_a_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) [RPM_SMD_SNOC_CLK] = &msm8974_snoc_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) [RPM_SMD_SNOC_A_CLK] = &msm8974_snoc_a_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) [RPM_SMD_CNOC_CLK] = &msm8974_cnoc_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) [RPM_SMD_CNOC_A_CLK] = &msm8974_cnoc_a_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) [RPM_SMD_MMSSNOC_AHB_CLK] = &msm8974_mmssnoc_ahb_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) [RPM_SMD_MMSSNOC_AHB_A_CLK] = &msm8974_mmssnoc_ahb_a_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) [RPM_SMD_BIMC_CLK] = &msm8974_bimc_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) [RPM_SMD_GFX3D_CLK_SRC] = &msm8974_gfx3d_clk_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) [RPM_SMD_GFX3D_A_CLK_SRC] = &msm8974_gfx3d_a_clk_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) [RPM_SMD_BIMC_A_CLK] = &msm8974_bimc_a_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) [RPM_SMD_OCMEMGX_CLK] = &msm8974_ocmemgx_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) [RPM_SMD_OCMEMGX_A_CLK] = &msm8974_ocmemgx_a_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) [RPM_SMD_QDSS_CLK] = &msm8974_qdss_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) [RPM_SMD_QDSS_A_CLK] = &msm8974_qdss_a_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) [RPM_SMD_CXO_D0] = &msm8974_cxo_d0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) [RPM_SMD_CXO_D0_A] = &msm8974_cxo_d0_a,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) [RPM_SMD_CXO_D1] = &msm8974_cxo_d1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) [RPM_SMD_CXO_D1_A] = &msm8974_cxo_d1_a,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) [RPM_SMD_CXO_A0] = &msm8974_cxo_a0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) [RPM_SMD_CXO_A0_A] = &msm8974_cxo_a0_a,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) [RPM_SMD_CXO_A1] = &msm8974_cxo_a1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) [RPM_SMD_CXO_A1_A] = &msm8974_cxo_a1_a,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) [RPM_SMD_CXO_A2] = &msm8974_cxo_a2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) [RPM_SMD_CXO_A2_A] = &msm8974_cxo_a2_a,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) [RPM_SMD_DIFF_CLK] = &msm8974_diff_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) [RPM_SMD_DIFF_A_CLK] = &msm8974_diff_a_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) [RPM_SMD_DIV_CLK1] = &msm8974_div_clk1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) [RPM_SMD_DIV_A_CLK1] = &msm8974_div_a_clk1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) [RPM_SMD_DIV_CLK2] = &msm8974_div_clk2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) [RPM_SMD_DIV_A_CLK2] = &msm8974_div_a_clk2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) [RPM_SMD_CXO_D0_PIN] = &msm8974_cxo_d0_pin,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) [RPM_SMD_CXO_D0_A_PIN] = &msm8974_cxo_d0_a_pin,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) [RPM_SMD_CXO_D1_PIN] = &msm8974_cxo_d1_pin,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) [RPM_SMD_CXO_D1_A_PIN] = &msm8974_cxo_d1_a_pin,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) [RPM_SMD_CXO_A0_PIN] = &msm8974_cxo_a0_pin,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) [RPM_SMD_CXO_A0_A_PIN] = &msm8974_cxo_a0_a_pin,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) [RPM_SMD_CXO_A1_PIN] = &msm8974_cxo_a1_pin,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) [RPM_SMD_CXO_A1_A_PIN] = &msm8974_cxo_a1_a_pin,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) [RPM_SMD_CXO_A2_PIN] = &msm8974_cxo_a2_pin,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) [RPM_SMD_CXO_A2_A_PIN] = &msm8974_cxo_a2_a_pin,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) static const struct rpm_smd_clk_desc rpm_clk_msm8974 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) .clks = msm8974_clks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) .num_clks = ARRAY_SIZE(msm8974_clks),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) /* msm8976 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) DEFINE_CLK_SMD_RPM(msm8976, pcnoc_clk, pcnoc_a_clk, QCOM_SMD_RPM_BUS_CLK, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) DEFINE_CLK_SMD_RPM(msm8976, snoc_clk, snoc_a_clk, QCOM_SMD_RPM_BUS_CLK, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) DEFINE_CLK_SMD_RPM(msm8976, mmssnoc_ahb_clk, mmssnoc_ahb_a_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) QCOM_SMD_RPM_BUS_CLK, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) DEFINE_CLK_SMD_RPM(msm8976, bimc_clk, bimc_a_clk, QCOM_SMD_RPM_MEM_CLK, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) DEFINE_CLK_SMD_RPM(msm8976, ipa_clk, ipa_a_clk, QCOM_SMD_RPM_IPA_CLK, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) DEFINE_CLK_SMD_RPM_QDSS(msm8976, qdss_clk, qdss_a_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) QCOM_SMD_RPM_MISC_CLK, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) DEFINE_CLK_SMD_RPM_XO_BUFFER(msm8976, bb_clk1, bb_clk1_a, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) DEFINE_CLK_SMD_RPM_XO_BUFFER(msm8976, bb_clk2, bb_clk2_a, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) DEFINE_CLK_SMD_RPM_XO_BUFFER(msm8976, rf_clk2, rf_clk2_a, 5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) DEFINE_CLK_SMD_RPM_XO_BUFFER(msm8976, div_clk2, div_clk2_a, 12);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(msm8976, bb_clk1_pin, bb_clk1_a_pin, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(msm8976, bb_clk2_pin, bb_clk2_a_pin, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) static struct clk_smd_rpm *msm8976_clks[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) [RPM_SMD_PCNOC_CLK] = &msm8976_pcnoc_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) [RPM_SMD_PCNOC_A_CLK] = &msm8976_pcnoc_a_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) [RPM_SMD_SNOC_CLK] = &msm8976_snoc_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) [RPM_SMD_SNOC_A_CLK] = &msm8976_snoc_a_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) [RPM_SMD_BIMC_CLK] = &msm8976_bimc_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) [RPM_SMD_BIMC_A_CLK] = &msm8976_bimc_a_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) [RPM_SMD_QDSS_CLK] = &msm8976_qdss_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) [RPM_SMD_QDSS_A_CLK] = &msm8976_qdss_a_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) [RPM_SMD_BB_CLK1] = &msm8976_bb_clk1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) [RPM_SMD_BB_CLK1_A] = &msm8976_bb_clk1_a,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) [RPM_SMD_BB_CLK2] = &msm8976_bb_clk2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) [RPM_SMD_BB_CLK2_A] = &msm8976_bb_clk2_a,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) [RPM_SMD_RF_CLK2] = &msm8976_rf_clk2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) [RPM_SMD_RF_CLK2_A] = &msm8976_rf_clk2_a,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) [RPM_SMD_BB_CLK1_PIN] = &msm8976_bb_clk1_pin,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) [RPM_SMD_BB_CLK1_A_PIN] = &msm8976_bb_clk1_a_pin,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) [RPM_SMD_BB_CLK2_PIN] = &msm8976_bb_clk2_pin,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) [RPM_SMD_BB_CLK2_A_PIN] = &msm8976_bb_clk2_a_pin,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) [RPM_SMD_MMSSNOC_AHB_CLK] = &msm8976_mmssnoc_ahb_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) [RPM_SMD_MMSSNOC_AHB_A_CLK] = &msm8976_mmssnoc_ahb_a_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) [RPM_SMD_DIV_CLK2] = &msm8976_div_clk2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) [RPM_SMD_DIV_A_CLK2] = &msm8976_div_clk2_a,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) [RPM_SMD_IPA_CLK] = &msm8976_ipa_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) [RPM_SMD_IPA_A_CLK] = &msm8976_ipa_a_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) static const struct rpm_smd_clk_desc rpm_clk_msm8976 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) .clks = msm8976_clks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) .num_clks = ARRAY_SIZE(msm8976_clks),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) /* msm8992 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) DEFINE_CLK_SMD_RPM(msm8992, pnoc_clk, pnoc_a_clk, QCOM_SMD_RPM_BUS_CLK, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) DEFINE_CLK_SMD_RPM(msm8992, ocmemgx_clk, ocmemgx_a_clk, QCOM_SMD_RPM_MEM_CLK, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) DEFINE_CLK_SMD_RPM(msm8992, bimc_clk, bimc_a_clk, QCOM_SMD_RPM_MEM_CLK, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) DEFINE_CLK_SMD_RPM(msm8992, cnoc_clk, cnoc_a_clk, QCOM_SMD_RPM_BUS_CLK, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) DEFINE_CLK_SMD_RPM(msm8992, gfx3d_clk_src, gfx3d_a_clk_src, QCOM_SMD_RPM_MEM_CLK, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) DEFINE_CLK_SMD_RPM(msm8992, snoc_clk, snoc_a_clk, QCOM_SMD_RPM_BUS_CLK, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) DEFINE_CLK_SMD_RPM_XO_BUFFER(msm8992, bb_clk1, bb_clk1_a, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(msm8992, bb_clk1_pin, bb_clk1_a_pin, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) DEFINE_CLK_SMD_RPM_XO_BUFFER(msm8992, bb_clk2, bb_clk2_a, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(msm8992, bb_clk2_pin, bb_clk2_a_pin, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) DEFINE_CLK_SMD_RPM_XO_BUFFER(msm8992, div_clk1, div_clk1_a, 11);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) DEFINE_CLK_SMD_RPM_XO_BUFFER(msm8992, div_clk2, div_clk2_a, 12);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) DEFINE_CLK_SMD_RPM_XO_BUFFER(msm8992, div_clk3, div_clk3_a, 13);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) DEFINE_CLK_SMD_RPM(msm8992, ipa_clk, ipa_a_clk, QCOM_SMD_RPM_IPA_CLK, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) DEFINE_CLK_SMD_RPM_XO_BUFFER(msm8992, ln_bb_clk, ln_bb_a_clk, 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) DEFINE_CLK_SMD_RPM(msm8992, mmssnoc_ahb_clk, mmssnoc_ahb_a_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) QCOM_SMD_RPM_BUS_CLK, 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) DEFINE_CLK_SMD_RPM_QDSS(msm8992, qdss_clk, qdss_a_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) QCOM_SMD_RPM_MISC_CLK, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) DEFINE_CLK_SMD_RPM_XO_BUFFER(msm8992, rf_clk1, rf_clk1_a, 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) DEFINE_CLK_SMD_RPM_XO_BUFFER(msm8992, rf_clk2, rf_clk2_a, 5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(msm8992, rf_clk1_pin, rf_clk1_a_pin, 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(msm8992, rf_clk2_pin, rf_clk2_a_pin, 5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) DEFINE_CLK_SMD_RPM(msm8992, ce1_clk, ce1_a_clk, QCOM_SMD_RPM_CE_CLK, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) DEFINE_CLK_SMD_RPM(msm8992, ce2_clk, ce2_a_clk, QCOM_SMD_RPM_CE_CLK, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) static struct clk_smd_rpm *msm8992_clks[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) [RPM_SMD_PNOC_CLK] = &msm8992_pnoc_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) [RPM_SMD_PNOC_A_CLK] = &msm8992_pnoc_a_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) [RPM_SMD_OCMEMGX_CLK] = &msm8992_ocmemgx_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) [RPM_SMD_OCMEMGX_A_CLK] = &msm8992_ocmemgx_a_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) [RPM_SMD_BIMC_CLK] = &msm8992_bimc_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) [RPM_SMD_BIMC_A_CLK] = &msm8992_bimc_a_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) [RPM_SMD_CNOC_CLK] = &msm8992_cnoc_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) [RPM_SMD_CNOC_A_CLK] = &msm8992_cnoc_a_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) [RPM_SMD_GFX3D_CLK_SRC] = &msm8992_gfx3d_clk_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) [RPM_SMD_GFX3D_A_CLK_SRC] = &msm8992_gfx3d_a_clk_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) [RPM_SMD_SNOC_CLK] = &msm8992_snoc_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) [RPM_SMD_SNOC_A_CLK] = &msm8992_snoc_a_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) [RPM_SMD_BB_CLK1] = &msm8992_bb_clk1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) [RPM_SMD_BB_CLK1_A] = &msm8992_bb_clk1_a,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) [RPM_SMD_BB_CLK1_PIN] = &msm8992_bb_clk1_pin,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) [RPM_SMD_BB_CLK1_A_PIN] = &msm8992_bb_clk1_a_pin,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) [RPM_SMD_BB_CLK2] = &msm8992_bb_clk2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) [RPM_SMD_BB_CLK2_A] = &msm8992_bb_clk2_a,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) [RPM_SMD_BB_CLK2_PIN] = &msm8992_bb_clk2_pin,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) [RPM_SMD_BB_CLK2_A_PIN] = &msm8992_bb_clk2_a_pin,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) [RPM_SMD_DIV_CLK1] = &msm8992_div_clk1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) [RPM_SMD_DIV_A_CLK1] = &msm8992_div_clk1_a,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) [RPM_SMD_DIV_CLK2] = &msm8992_div_clk2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) [RPM_SMD_DIV_A_CLK2] = &msm8992_div_clk2_a,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) [RPM_SMD_DIV_CLK3] = &msm8992_div_clk3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) [RPM_SMD_DIV_A_CLK3] = &msm8992_div_clk3_a,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) [RPM_SMD_IPA_CLK] = &msm8992_ipa_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) [RPM_SMD_IPA_A_CLK] = &msm8992_ipa_a_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) [RPM_SMD_LN_BB_CLK] = &msm8992_ln_bb_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) [RPM_SMD_LN_BB_A_CLK] = &msm8992_ln_bb_a_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) [RPM_SMD_MMSSNOC_AHB_CLK] = &msm8992_mmssnoc_ahb_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) [RPM_SMD_MMSSNOC_AHB_A_CLK] = &msm8992_mmssnoc_ahb_a_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) [RPM_SMD_QDSS_CLK] = &msm8992_qdss_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) [RPM_SMD_QDSS_A_CLK] = &msm8992_qdss_a_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) [RPM_SMD_RF_CLK1] = &msm8992_rf_clk1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) [RPM_SMD_RF_CLK1_A] = &msm8992_rf_clk1_a,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) [RPM_SMD_RF_CLK2] = &msm8992_rf_clk2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) [RPM_SMD_RF_CLK2_A] = &msm8992_rf_clk2_a,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) [RPM_SMD_RF_CLK1_PIN] = &msm8992_rf_clk1_pin,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) [RPM_SMD_RF_CLK1_A_PIN] = &msm8992_rf_clk1_a_pin,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) [RPM_SMD_RF_CLK2_PIN] = &msm8992_rf_clk2_pin,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) [RPM_SMD_RF_CLK2_A_PIN] = &msm8992_rf_clk2_a_pin,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) [RPM_SMD_CE1_CLK] = &msm8992_ce1_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) [RPM_SMD_CE1_A_CLK] = &msm8992_ce1_a_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) [RPM_SMD_CE2_CLK] = &msm8992_ce2_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) [RPM_SMD_CE2_A_CLK] = &msm8992_ce2_a_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) static const struct rpm_smd_clk_desc rpm_clk_msm8992 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) .clks = msm8992_clks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) .num_clks = ARRAY_SIZE(msm8992_clks),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) /* msm8994 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) DEFINE_CLK_SMD_RPM(msm8994, pnoc_clk, pnoc_a_clk, QCOM_SMD_RPM_BUS_CLK, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) DEFINE_CLK_SMD_RPM(msm8994, ocmemgx_clk, ocmemgx_a_clk, QCOM_SMD_RPM_MEM_CLK, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) DEFINE_CLK_SMD_RPM(msm8994, bimc_clk, bimc_a_clk, QCOM_SMD_RPM_MEM_CLK, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) DEFINE_CLK_SMD_RPM(msm8994, cnoc_clk, cnoc_a_clk, QCOM_SMD_RPM_BUS_CLK, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) DEFINE_CLK_SMD_RPM(msm8994, gfx3d_clk_src, gfx3d_a_clk_src, QCOM_SMD_RPM_MEM_CLK, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) DEFINE_CLK_SMD_RPM(msm8994, snoc_clk, snoc_a_clk, QCOM_SMD_RPM_BUS_CLK, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) DEFINE_CLK_SMD_RPM_XO_BUFFER(msm8994, bb_clk1, bb_clk1_a, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(msm8994, bb_clk1_pin, bb_clk1_a_pin, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) DEFINE_CLK_SMD_RPM_XO_BUFFER(msm8994, bb_clk2, bb_clk2_a, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(msm8994, bb_clk2_pin, bb_clk2_a_pin, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) DEFINE_CLK_SMD_RPM_XO_BUFFER(msm8994, div_clk1, div_clk1_a, 11);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) DEFINE_CLK_SMD_RPM_XO_BUFFER(msm8994, div_clk2, div_clk2_a, 12);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) DEFINE_CLK_SMD_RPM_XO_BUFFER(msm8994, div_clk3, div_clk3_a, 13);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) DEFINE_CLK_SMD_RPM(msm8994, ipa_clk, ipa_a_clk, QCOM_SMD_RPM_IPA_CLK, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) DEFINE_CLK_SMD_RPM_XO_BUFFER(msm8994, ln_bb_clk, ln_bb_a_clk, 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) DEFINE_CLK_SMD_RPM(msm8994, mmssnoc_ahb_clk, mmssnoc_ahb_a_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) QCOM_SMD_RPM_BUS_CLK, 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) DEFINE_CLK_SMD_RPM_QDSS(msm8994, qdss_clk, qdss_a_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) QCOM_SMD_RPM_MISC_CLK, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) DEFINE_CLK_SMD_RPM_XO_BUFFER(msm8994, rf_clk1, rf_clk1_a, 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) DEFINE_CLK_SMD_RPM_XO_BUFFER(msm8994, rf_clk2, rf_clk2_a, 5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(msm8994, rf_clk1_pin, rf_clk1_a_pin, 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(msm8994, rf_clk2_pin, rf_clk2_a_pin, 5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) DEFINE_CLK_SMD_RPM(msm8994, ce1_clk, ce1_a_clk, QCOM_SMD_RPM_CE_CLK, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) DEFINE_CLK_SMD_RPM(msm8994, ce2_clk, ce2_a_clk, QCOM_SMD_RPM_CE_CLK, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) DEFINE_CLK_SMD_RPM(msm8994, ce3_clk, ce3_a_clk, QCOM_SMD_RPM_CE_CLK, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) static struct clk_smd_rpm *msm8994_clks[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) [RPM_SMD_PNOC_CLK] = &msm8994_pnoc_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) [RPM_SMD_PNOC_A_CLK] = &msm8994_pnoc_a_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) [RPM_SMD_OCMEMGX_CLK] = &msm8994_ocmemgx_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) [RPM_SMD_OCMEMGX_A_CLK] = &msm8994_ocmemgx_a_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) [RPM_SMD_BIMC_CLK] = &msm8994_bimc_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) [RPM_SMD_BIMC_A_CLK] = &msm8994_bimc_a_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) [RPM_SMD_CNOC_CLK] = &msm8994_cnoc_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) [RPM_SMD_CNOC_A_CLK] = &msm8994_cnoc_a_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) [RPM_SMD_GFX3D_CLK_SRC] = &msm8994_gfx3d_clk_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) [RPM_SMD_GFX3D_A_CLK_SRC] = &msm8994_gfx3d_a_clk_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) [RPM_SMD_SNOC_CLK] = &msm8994_snoc_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) [RPM_SMD_SNOC_A_CLK] = &msm8994_snoc_a_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) [RPM_SMD_BB_CLK1] = &msm8994_bb_clk1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) [RPM_SMD_BB_CLK1_A] = &msm8994_bb_clk1_a,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) [RPM_SMD_BB_CLK1_PIN] = &msm8994_bb_clk1_pin,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) [RPM_SMD_BB_CLK1_A_PIN] = &msm8994_bb_clk1_a_pin,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) [RPM_SMD_BB_CLK2] = &msm8994_bb_clk2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) [RPM_SMD_BB_CLK2_A] = &msm8994_bb_clk2_a,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) [RPM_SMD_BB_CLK2_PIN] = &msm8994_bb_clk2_pin,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) [RPM_SMD_BB_CLK2_A_PIN] = &msm8994_bb_clk2_a_pin,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) [RPM_SMD_DIV_CLK1] = &msm8994_div_clk1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) [RPM_SMD_DIV_A_CLK1] = &msm8994_div_clk1_a,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) [RPM_SMD_DIV_CLK2] = &msm8994_div_clk2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) [RPM_SMD_DIV_A_CLK2] = &msm8994_div_clk2_a,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) [RPM_SMD_DIV_CLK3] = &msm8994_div_clk3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) [RPM_SMD_DIV_A_CLK3] = &msm8994_div_clk3_a,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) [RPM_SMD_IPA_CLK] = &msm8994_ipa_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) [RPM_SMD_IPA_A_CLK] = &msm8994_ipa_a_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) [RPM_SMD_LN_BB_CLK] = &msm8994_ln_bb_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) [RPM_SMD_LN_BB_A_CLK] = &msm8994_ln_bb_a_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) [RPM_SMD_MMSSNOC_AHB_CLK] = &msm8994_mmssnoc_ahb_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) [RPM_SMD_MMSSNOC_AHB_A_CLK] = &msm8994_mmssnoc_ahb_a_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) [RPM_SMD_QDSS_CLK] = &msm8994_qdss_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) [RPM_SMD_QDSS_A_CLK] = &msm8994_qdss_a_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) [RPM_SMD_RF_CLK1] = &msm8994_rf_clk1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) [RPM_SMD_RF_CLK1_A] = &msm8994_rf_clk1_a,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) [RPM_SMD_RF_CLK2] = &msm8994_rf_clk2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) [RPM_SMD_RF_CLK2_A] = &msm8994_rf_clk2_a,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) [RPM_SMD_RF_CLK1_PIN] = &msm8994_rf_clk1_pin,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) [RPM_SMD_RF_CLK1_A_PIN] = &msm8994_rf_clk1_a_pin,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) [RPM_SMD_RF_CLK2_PIN] = &msm8994_rf_clk2_pin,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) [RPM_SMD_RF_CLK2_A_PIN] = &msm8994_rf_clk2_a_pin,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) [RPM_SMD_CE1_CLK] = &msm8994_ce1_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) [RPM_SMD_CE1_A_CLK] = &msm8994_ce1_a_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) [RPM_SMD_CE2_CLK] = &msm8994_ce2_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) [RPM_SMD_CE2_A_CLK] = &msm8994_ce2_a_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) [RPM_SMD_CE3_CLK] = &msm8994_ce3_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) [RPM_SMD_CE3_A_CLK] = &msm8994_ce3_a_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) static const struct rpm_smd_clk_desc rpm_clk_msm8994 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) .clks = msm8994_clks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) .num_clks = ARRAY_SIZE(msm8994_clks),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) /* msm8996 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) DEFINE_CLK_SMD_RPM(msm8996, pcnoc_clk, pcnoc_a_clk, QCOM_SMD_RPM_BUS_CLK, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) DEFINE_CLK_SMD_RPM(msm8996, snoc_clk, snoc_a_clk, QCOM_SMD_RPM_BUS_CLK, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) DEFINE_CLK_SMD_RPM(msm8996, cnoc_clk, cnoc_a_clk, QCOM_SMD_RPM_BUS_CLK, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) DEFINE_CLK_SMD_RPM(msm8996, bimc_clk, bimc_a_clk, QCOM_SMD_RPM_MEM_CLK, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) DEFINE_CLK_SMD_RPM(msm8996, mmssnoc_axi_rpm_clk, mmssnoc_axi_rpm_a_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) QCOM_SMD_RPM_MMAXI_CLK, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) DEFINE_CLK_SMD_RPM(msm8996, ipa_clk, ipa_a_clk, QCOM_SMD_RPM_IPA_CLK, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) DEFINE_CLK_SMD_RPM(msm8996, ce1_clk, ce1_a_clk, QCOM_SMD_RPM_CE_CLK, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) DEFINE_CLK_SMD_RPM_BRANCH(msm8996, aggre1_noc_clk, aggre1_noc_a_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) QCOM_SMD_RPM_AGGR_CLK, 1, 1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) DEFINE_CLK_SMD_RPM_BRANCH(msm8996, aggre2_noc_clk, aggre2_noc_a_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) QCOM_SMD_RPM_AGGR_CLK, 2, 1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) DEFINE_CLK_SMD_RPM_QDSS(msm8996, qdss_clk, qdss_a_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) QCOM_SMD_RPM_MISC_CLK, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) DEFINE_CLK_SMD_RPM_XO_BUFFER(msm8996, bb_clk1, bb_clk1_a, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) DEFINE_CLK_SMD_RPM_XO_BUFFER(msm8996, bb_clk2, bb_clk2_a, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) DEFINE_CLK_SMD_RPM_XO_BUFFER(msm8996, rf_clk1, rf_clk1_a, 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) DEFINE_CLK_SMD_RPM_XO_BUFFER(msm8996, rf_clk2, rf_clk2_a, 5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) DEFINE_CLK_SMD_RPM_XO_BUFFER(msm8996, ln_bb_clk, ln_bb_a_clk, 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) DEFINE_CLK_SMD_RPM_XO_BUFFER(msm8996, div_clk1, div_clk1_a, 0xb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) DEFINE_CLK_SMD_RPM_XO_BUFFER(msm8996, div_clk2, div_clk2_a, 0xc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) DEFINE_CLK_SMD_RPM_XO_BUFFER(msm8996, div_clk3, div_clk3_a, 0xd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(msm8996, bb_clk1_pin, bb_clk1_a_pin, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(msm8996, bb_clk2_pin, bb_clk2_a_pin, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(msm8996, rf_clk1_pin, rf_clk1_a_pin, 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(msm8996, rf_clk2_pin, rf_clk2_a_pin, 5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) static struct clk_smd_rpm *msm8996_clks[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) [RPM_SMD_PCNOC_CLK] = &msm8996_pcnoc_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) [RPM_SMD_PCNOC_A_CLK] = &msm8996_pcnoc_a_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) [RPM_SMD_SNOC_CLK] = &msm8996_snoc_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) [RPM_SMD_SNOC_A_CLK] = &msm8996_snoc_a_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) [RPM_SMD_CNOC_CLK] = &msm8996_cnoc_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) [RPM_SMD_CNOC_A_CLK] = &msm8996_cnoc_a_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) [RPM_SMD_BIMC_CLK] = &msm8996_bimc_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) [RPM_SMD_BIMC_A_CLK] = &msm8996_bimc_a_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) [RPM_SMD_MMAXI_CLK] = &msm8996_mmssnoc_axi_rpm_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) [RPM_SMD_MMAXI_A_CLK] = &msm8996_mmssnoc_axi_rpm_a_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) [RPM_SMD_IPA_CLK] = &msm8996_ipa_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) [RPM_SMD_IPA_A_CLK] = &msm8996_ipa_a_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) [RPM_SMD_CE1_CLK] = &msm8996_ce1_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) [RPM_SMD_CE1_A_CLK] = &msm8996_ce1_a_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) [RPM_SMD_AGGR1_NOC_CLK] = &msm8996_aggre1_noc_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) [RPM_SMD_AGGR1_NOC_A_CLK] = &msm8996_aggre1_noc_a_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) [RPM_SMD_AGGR2_NOC_CLK] = &msm8996_aggre2_noc_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) [RPM_SMD_AGGR2_NOC_A_CLK] = &msm8996_aggre2_noc_a_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) [RPM_SMD_QDSS_CLK] = &msm8996_qdss_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) [RPM_SMD_QDSS_A_CLK] = &msm8996_qdss_a_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) [RPM_SMD_BB_CLK1] = &msm8996_bb_clk1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) [RPM_SMD_BB_CLK1_A] = &msm8996_bb_clk1_a,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) [RPM_SMD_BB_CLK2] = &msm8996_bb_clk2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) [RPM_SMD_BB_CLK2_A] = &msm8996_bb_clk2_a,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) [RPM_SMD_RF_CLK1] = &msm8996_rf_clk1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) [RPM_SMD_RF_CLK1_A] = &msm8996_rf_clk1_a,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) [RPM_SMD_RF_CLK2] = &msm8996_rf_clk2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) [RPM_SMD_RF_CLK2_A] = &msm8996_rf_clk2_a,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) [RPM_SMD_LN_BB_CLK] = &msm8996_ln_bb_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) [RPM_SMD_LN_BB_A_CLK] = &msm8996_ln_bb_a_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) [RPM_SMD_DIV_CLK1] = &msm8996_div_clk1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) [RPM_SMD_DIV_A_CLK1] = &msm8996_div_clk1_a,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) [RPM_SMD_DIV_CLK2] = &msm8996_div_clk2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) [RPM_SMD_DIV_A_CLK2] = &msm8996_div_clk2_a,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) [RPM_SMD_DIV_CLK3] = &msm8996_div_clk3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) [RPM_SMD_DIV_A_CLK3] = &msm8996_div_clk3_a,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) [RPM_SMD_BB_CLK1_PIN] = &msm8996_bb_clk1_pin,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) [RPM_SMD_BB_CLK1_A_PIN] = &msm8996_bb_clk1_a_pin,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) [RPM_SMD_BB_CLK2_PIN] = &msm8996_bb_clk2_pin,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) [RPM_SMD_BB_CLK2_A_PIN] = &msm8996_bb_clk2_a_pin,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) [RPM_SMD_RF_CLK1_PIN] = &msm8996_rf_clk1_pin,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) [RPM_SMD_RF_CLK1_A_PIN] = &msm8996_rf_clk1_a_pin,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) [RPM_SMD_RF_CLK2_PIN] = &msm8996_rf_clk2_pin,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) [RPM_SMD_RF_CLK2_A_PIN] = &msm8996_rf_clk2_a_pin,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) static const struct rpm_smd_clk_desc rpm_clk_msm8996 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) .clks = msm8996_clks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) .num_clks = ARRAY_SIZE(msm8996_clks),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) /* QCS404 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) DEFINE_CLK_SMD_RPM_QDSS(qcs404, qdss_clk, qdss_a_clk, QCOM_SMD_RPM_MISC_CLK, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) DEFINE_CLK_SMD_RPM(qcs404, pnoc_clk, pnoc_a_clk, QCOM_SMD_RPM_BUS_CLK, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) DEFINE_CLK_SMD_RPM(qcs404, snoc_clk, snoc_a_clk, QCOM_SMD_RPM_BUS_CLK, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) DEFINE_CLK_SMD_RPM(qcs404, bimc_clk, bimc_a_clk, QCOM_SMD_RPM_MEM_CLK, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) DEFINE_CLK_SMD_RPM(qcs404, bimc_gpu_clk, bimc_gpu_a_clk, QCOM_SMD_RPM_MEM_CLK, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) DEFINE_CLK_SMD_RPM(qcs404, qpic_clk, qpic_a_clk, QCOM_SMD_RPM_QPIC_CLK, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) DEFINE_CLK_SMD_RPM(qcs404, ce1_clk, ce1_a_clk, QCOM_SMD_RPM_CE_CLK, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) DEFINE_CLK_SMD_RPM_XO_BUFFER(qcs404, rf_clk1, rf_clk1_a, 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(qcs404, rf_clk1_pin, rf_clk1_a_pin, 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) DEFINE_CLK_SMD_RPM_XO_BUFFER(qcs404, ln_bb_clk, ln_bb_a_clk, 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(qcs404, ln_bb_clk_pin, ln_bb_clk_a_pin, 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) static struct clk_smd_rpm *qcs404_clks[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) [RPM_SMD_QDSS_CLK] = &qcs404_qdss_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) [RPM_SMD_QDSS_A_CLK] = &qcs404_qdss_a_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) [RPM_SMD_PNOC_CLK] = &qcs404_pnoc_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) [RPM_SMD_PNOC_A_CLK] = &qcs404_pnoc_a_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) [RPM_SMD_SNOC_CLK] = &qcs404_snoc_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) [RPM_SMD_SNOC_A_CLK] = &qcs404_snoc_a_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) [RPM_SMD_BIMC_CLK] = &qcs404_bimc_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) [RPM_SMD_BIMC_A_CLK] = &qcs404_bimc_a_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) [RPM_SMD_BIMC_GPU_CLK] = &qcs404_bimc_gpu_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) [RPM_SMD_BIMC_GPU_A_CLK] = &qcs404_bimc_gpu_a_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) [RPM_SMD_QPIC_CLK] = &qcs404_qpic_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) [RPM_SMD_QPIC_CLK_A] = &qcs404_qpic_a_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) [RPM_SMD_CE1_CLK] = &qcs404_ce1_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) [RPM_SMD_CE1_A_CLK] = &qcs404_ce1_a_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) [RPM_SMD_RF_CLK1] = &qcs404_rf_clk1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) [RPM_SMD_RF_CLK1_A] = &qcs404_rf_clk1_a,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) [RPM_SMD_LN_BB_CLK] = &qcs404_ln_bb_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) [RPM_SMD_LN_BB_A_CLK] = &qcs404_ln_bb_a_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) static const struct rpm_smd_clk_desc rpm_clk_qcs404 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) .clks = qcs404_clks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) .num_clks = ARRAY_SIZE(qcs404_clks),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) /* msm8998 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) DEFINE_CLK_SMD_RPM(msm8998, bimc_clk, bimc_a_clk, QCOM_SMD_RPM_MEM_CLK, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) DEFINE_CLK_SMD_RPM(msm8998, pcnoc_clk, pcnoc_a_clk, QCOM_SMD_RPM_BUS_CLK, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) DEFINE_CLK_SMD_RPM(msm8998, snoc_clk, snoc_a_clk, QCOM_SMD_RPM_BUS_CLK, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) DEFINE_CLK_SMD_RPM(msm8998, cnoc_clk, cnoc_a_clk, QCOM_SMD_RPM_BUS_CLK, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) DEFINE_CLK_SMD_RPM(msm8998, ce1_clk, ce1_a_clk, QCOM_SMD_RPM_CE_CLK, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) DEFINE_CLK_SMD_RPM_XO_BUFFER(msm8998, div_clk1, div_clk1_a, 0xb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) DEFINE_CLK_SMD_RPM(msm8998, ipa_clk, ipa_a_clk, QCOM_SMD_RPM_IPA_CLK, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) DEFINE_CLK_SMD_RPM_XO_BUFFER(msm8998, ln_bb_clk1, ln_bb_clk1_a, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) DEFINE_CLK_SMD_RPM_XO_BUFFER(msm8998, ln_bb_clk2, ln_bb_clk2_a, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(msm8998, ln_bb_clk3_pin, ln_bb_clk3_a_pin,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) DEFINE_CLK_SMD_RPM(msm8998, mmssnoc_axi_rpm_clk, mmssnoc_axi_rpm_a_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) QCOM_SMD_RPM_MMAXI_CLK, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) DEFINE_CLK_SMD_RPM(msm8998, aggre1_noc_clk, aggre1_noc_a_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) QCOM_SMD_RPM_AGGR_CLK, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) DEFINE_CLK_SMD_RPM(msm8998, aggre2_noc_clk, aggre2_noc_a_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) QCOM_SMD_RPM_AGGR_CLK, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) DEFINE_CLK_SMD_RPM_QDSS(msm8998, qdss_clk, qdss_a_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) QCOM_SMD_RPM_MISC_CLK, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) DEFINE_CLK_SMD_RPM_XO_BUFFER(msm8998, rf_clk1, rf_clk1_a, 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(msm8998, rf_clk2_pin, rf_clk2_a_pin, 5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) DEFINE_CLK_SMD_RPM_XO_BUFFER(msm8998, rf_clk3, rf_clk3_a, 6);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(msm8998, rf_clk3_pin, rf_clk3_a_pin, 6);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) static struct clk_smd_rpm *msm8998_clks[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) [RPM_SMD_BIMC_CLK] = &msm8998_bimc_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) [RPM_SMD_BIMC_A_CLK] = &msm8998_bimc_a_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) [RPM_SMD_PCNOC_CLK] = &msm8998_pcnoc_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) [RPM_SMD_PCNOC_A_CLK] = &msm8998_pcnoc_a_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) [RPM_SMD_SNOC_CLK] = &msm8998_snoc_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) [RPM_SMD_SNOC_A_CLK] = &msm8998_snoc_a_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) [RPM_SMD_CNOC_CLK] = &msm8998_cnoc_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) [RPM_SMD_CNOC_A_CLK] = &msm8998_cnoc_a_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) [RPM_SMD_CE1_CLK] = &msm8998_ce1_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) [RPM_SMD_CE1_A_CLK] = &msm8998_ce1_a_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) [RPM_SMD_DIV_CLK1] = &msm8998_div_clk1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) [RPM_SMD_DIV_A_CLK1] = &msm8998_div_clk1_a,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) [RPM_SMD_IPA_CLK] = &msm8998_ipa_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) [RPM_SMD_IPA_A_CLK] = &msm8998_ipa_a_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) [RPM_SMD_LN_BB_CLK1] = &msm8998_ln_bb_clk1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) [RPM_SMD_LN_BB_CLK1_A] = &msm8998_ln_bb_clk1_a,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) [RPM_SMD_LN_BB_CLK2] = &msm8998_ln_bb_clk2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) [RPM_SMD_LN_BB_CLK2_A] = &msm8998_ln_bb_clk2_a,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) [RPM_SMD_LN_BB_CLK3_PIN] = &msm8998_ln_bb_clk3_pin,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) [RPM_SMD_LN_BB_CLK3_A_PIN] = &msm8998_ln_bb_clk3_a_pin,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) [RPM_SMD_MMAXI_CLK] = &msm8998_mmssnoc_axi_rpm_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) [RPM_SMD_MMAXI_A_CLK] = &msm8998_mmssnoc_axi_rpm_a_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) [RPM_SMD_AGGR1_NOC_CLK] = &msm8998_aggre1_noc_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) [RPM_SMD_AGGR1_NOC_A_CLK] = &msm8998_aggre1_noc_a_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) [RPM_SMD_AGGR2_NOC_CLK] = &msm8998_aggre2_noc_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) [RPM_SMD_AGGR2_NOC_A_CLK] = &msm8998_aggre2_noc_a_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) [RPM_SMD_QDSS_CLK] = &msm8998_qdss_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) [RPM_SMD_QDSS_A_CLK] = &msm8998_qdss_a_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) [RPM_SMD_RF_CLK1] = &msm8998_rf_clk1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) [RPM_SMD_RF_CLK1_A] = &msm8998_rf_clk1_a,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) [RPM_SMD_RF_CLK2_PIN] = &msm8998_rf_clk2_pin,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) [RPM_SMD_RF_CLK2_A_PIN] = &msm8998_rf_clk2_a_pin,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) [RPM_SMD_RF_CLK3] = &msm8998_rf_clk3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) [RPM_SMD_RF_CLK3_A] = &msm8998_rf_clk3_a,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) [RPM_SMD_RF_CLK3_PIN] = &msm8998_rf_clk3_pin,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) [RPM_SMD_RF_CLK3_A_PIN] = &msm8998_rf_clk3_a_pin,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) static const struct rpm_smd_clk_desc rpm_clk_msm8998 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) .clks = msm8998_clks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) .num_clks = ARRAY_SIZE(msm8998_clks),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) /* sdm660 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) DEFINE_CLK_SMD_RPM_BRANCH(sdm660, bi_tcxo, bi_tcxo_a, QCOM_SMD_RPM_MISC_CLK, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) 19200000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) DEFINE_CLK_SMD_RPM(sdm660, snoc_clk, snoc_a_clk, QCOM_SMD_RPM_BUS_CLK, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) DEFINE_CLK_SMD_RPM(sdm660, cnoc_clk, cnoc_a_clk, QCOM_SMD_RPM_BUS_CLK, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) DEFINE_CLK_SMD_RPM(sdm660, cnoc_periph_clk, cnoc_periph_a_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) QCOM_SMD_RPM_BUS_CLK, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) DEFINE_CLK_SMD_RPM(sdm660, bimc_clk, bimc_a_clk, QCOM_SMD_RPM_MEM_CLK, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) DEFINE_CLK_SMD_RPM(sdm660, mmssnoc_axi_clk, mmssnoc_axi_a_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) QCOM_SMD_RPM_MMAXI_CLK, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) DEFINE_CLK_SMD_RPM(sdm660, ipa_clk, ipa_a_clk, QCOM_SMD_RPM_IPA_CLK, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) DEFINE_CLK_SMD_RPM(sdm660, ce1_clk, ce1_a_clk, QCOM_SMD_RPM_CE_CLK, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) DEFINE_CLK_SMD_RPM(sdm660, aggre2_noc_clk, aggre2_noc_a_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) QCOM_SMD_RPM_AGGR_CLK, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) DEFINE_CLK_SMD_RPM_QDSS(sdm660, qdss_clk, qdss_a_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) QCOM_SMD_RPM_MISC_CLK, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) DEFINE_CLK_SMD_RPM_XO_BUFFER(sdm660, rf_clk1, rf_clk1_a, 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) DEFINE_CLK_SMD_RPM_XO_BUFFER(sdm660, div_clk1, div_clk1_a, 11);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) DEFINE_CLK_SMD_RPM_XO_BUFFER(sdm660, ln_bb_clk1, ln_bb_clk1_a, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) DEFINE_CLK_SMD_RPM_XO_BUFFER(sdm660, ln_bb_clk2, ln_bb_clk2_a, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) DEFINE_CLK_SMD_RPM_XO_BUFFER(sdm660, ln_bb_clk3, ln_bb_clk3_a, 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(sdm660, rf_clk1_pin, rf_clk1_a_pin, 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(sdm660, ln_bb_clk1_pin,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) ln_bb_clk1_pin_a, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(sdm660, ln_bb_clk2_pin,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) ln_bb_clk2_pin_a, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(sdm660, ln_bb_clk3_pin,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) ln_bb_clk3_pin_a, 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) static struct clk_smd_rpm *sdm660_clks[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) [RPM_SMD_XO_CLK_SRC] = &sdm660_bi_tcxo,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) [RPM_SMD_XO_A_CLK_SRC] = &sdm660_bi_tcxo_a,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) [RPM_SMD_SNOC_CLK] = &sdm660_snoc_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) [RPM_SMD_SNOC_A_CLK] = &sdm660_snoc_a_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) [RPM_SMD_CNOC_CLK] = &sdm660_cnoc_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) [RPM_SMD_CNOC_A_CLK] = &sdm660_cnoc_a_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) [RPM_SMD_CNOC_PERIPH_CLK] = &sdm660_cnoc_periph_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) [RPM_SMD_CNOC_PERIPH_A_CLK] = &sdm660_cnoc_periph_a_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) [RPM_SMD_BIMC_CLK] = &sdm660_bimc_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) [RPM_SMD_BIMC_A_CLK] = &sdm660_bimc_a_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) [RPM_SMD_MMSSNOC_AXI_CLK] = &sdm660_mmssnoc_axi_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) [RPM_SMD_MMSSNOC_AXI_CLK_A] = &sdm660_mmssnoc_axi_a_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) [RPM_SMD_IPA_CLK] = &sdm660_ipa_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) [RPM_SMD_IPA_A_CLK] = &sdm660_ipa_a_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) [RPM_SMD_CE1_CLK] = &sdm660_ce1_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) [RPM_SMD_CE1_A_CLK] = &sdm660_ce1_a_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) [RPM_SMD_AGGR2_NOC_CLK] = &sdm660_aggre2_noc_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) [RPM_SMD_AGGR2_NOC_A_CLK] = &sdm660_aggre2_noc_a_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) [RPM_SMD_QDSS_CLK] = &sdm660_qdss_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) [RPM_SMD_QDSS_A_CLK] = &sdm660_qdss_a_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) [RPM_SMD_RF_CLK1] = &sdm660_rf_clk1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) [RPM_SMD_RF_CLK1_A] = &sdm660_rf_clk1_a,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) [RPM_SMD_DIV_CLK1] = &sdm660_div_clk1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) [RPM_SMD_DIV_A_CLK1] = &sdm660_div_clk1_a,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) [RPM_SMD_LN_BB_CLK] = &sdm660_ln_bb_clk1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) [RPM_SMD_LN_BB_A_CLK] = &sdm660_ln_bb_clk1_a,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) [RPM_SMD_LN_BB_CLK2] = &sdm660_ln_bb_clk2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) [RPM_SMD_LN_BB_CLK2_A] = &sdm660_ln_bb_clk2_a,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) [RPM_SMD_LN_BB_CLK3] = &sdm660_ln_bb_clk3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) [RPM_SMD_LN_BB_CLK3_A] = &sdm660_ln_bb_clk3_a,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) [RPM_SMD_RF_CLK1_PIN] = &sdm660_rf_clk1_pin,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) [RPM_SMD_RF_CLK1_A_PIN] = &sdm660_rf_clk1_a_pin,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) [RPM_SMD_LN_BB_CLK1_PIN] = &sdm660_ln_bb_clk1_pin,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) [RPM_SMD_LN_BB_CLK1_A_PIN] = &sdm660_ln_bb_clk1_pin_a,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) [RPM_SMD_LN_BB_CLK2_PIN] = &sdm660_ln_bb_clk2_pin,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) [RPM_SMD_LN_BB_CLK2_A_PIN] = &sdm660_ln_bb_clk2_pin_a,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) [RPM_SMD_LN_BB_CLK3_PIN] = &sdm660_ln_bb_clk3_pin,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) [RPM_SMD_LN_BB_CLK3_A_PIN] = &sdm660_ln_bb_clk3_pin_a,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) static const struct rpm_smd_clk_desc rpm_clk_sdm660 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) .clks = sdm660_clks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) .num_clks = ARRAY_SIZE(sdm660_clks),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) static const struct of_device_id rpm_smd_clk_match_table[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) { .compatible = "qcom,rpmcc-msm8916", .data = &rpm_clk_msm8916 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) { .compatible = "qcom,rpmcc-msm8936", .data = &rpm_clk_msm8936 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) { .compatible = "qcom,rpmcc-msm8974", .data = &rpm_clk_msm8974 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) { .compatible = "qcom,rpmcc-msm8976", .data = &rpm_clk_msm8976 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) { .compatible = "qcom,rpmcc-msm8992", .data = &rpm_clk_msm8992 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) { .compatible = "qcom,rpmcc-msm8994", .data = &rpm_clk_msm8994 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) { .compatible = "qcom,rpmcc-msm8996", .data = &rpm_clk_msm8996 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) { .compatible = "qcom,rpmcc-msm8998", .data = &rpm_clk_msm8998 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) { .compatible = "qcom,rpmcc-qcs404", .data = &rpm_clk_qcs404 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) { .compatible = "qcom,rpmcc-sdm660", .data = &rpm_clk_sdm660 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) MODULE_DEVICE_TABLE(of, rpm_smd_clk_match_table);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) static struct clk_hw *qcom_smdrpm_clk_hw_get(struct of_phandle_args *clkspec,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) void *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) struct rpm_cc *rcc = data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) unsigned int idx = clkspec->args[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) if (idx >= rcc->num_clks) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) pr_err("%s: invalid index %u\n", __func__, idx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) return ERR_PTR(-EINVAL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) return rcc->clks[idx] ? &rcc->clks[idx]->hw : ERR_PTR(-ENOENT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) static int rpm_smd_clk_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) struct rpm_cc *rcc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) size_t num_clks, i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) struct qcom_smd_rpm *rpm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097) struct clk_smd_rpm **rpm_smd_clks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) const struct rpm_smd_clk_desc *desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100) rpm = dev_get_drvdata(pdev->dev.parent);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) if (!rpm) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) dev_err(&pdev->dev, "Unable to retrieve handle to RPM\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106) desc = of_device_get_match_data(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107) if (!desc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) rpm_smd_clks = desc->clks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) num_clks = desc->num_clks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113) rcc = devm_kzalloc(&pdev->dev, sizeof(*rcc), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114) if (!rcc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) rcc->clks = rpm_smd_clks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118) rcc->num_clks = num_clks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120) for (i = 0; i < num_clks; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121) if (!rpm_smd_clks[i])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124) rpm_smd_clks[i]->rpm = rpm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) ret = clk_smd_rpm_handoff(rpm_smd_clks[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131) ret = clk_smd_rpm_enable_scaling(rpm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135) for (i = 0; i < num_clks; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136) if (!rpm_smd_clks[i])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139) ret = devm_clk_hw_register(&pdev->dev, &rpm_smd_clks[i]->hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144) ret = devm_of_clk_add_hw_provider(&pdev->dev, qcom_smdrpm_clk_hw_get,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145) rcc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150) err:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151) dev_err(&pdev->dev, "Error registering SMD clock driver (%d)\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155) static struct platform_driver rpm_smd_clk_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157) .name = "qcom-clk-smd-rpm",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158) .of_match_table = rpm_smd_clk_match_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160) .probe = rpm_smd_clk_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163) static int __init rpm_smd_clk_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165) return platform_driver_register(&rpm_smd_clk_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167) core_initcall(rpm_smd_clk_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169) static void __exit rpm_smd_clk_exit(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171) platform_driver_unregister(&rpm_smd_clk_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173) module_exit(rpm_smd_clk_exit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175) MODULE_DESCRIPTION("Qualcomm RPM over SMD Clock Controller Driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176) MODULE_LICENSE("GPL v2");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177) MODULE_ALIAS("platform:qcom-clk-smd-rpm");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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