^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (c) 2018-2020, The Linux Foundation. All rights reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) #include <linux/clk-provider.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/of_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <soc/qcom/cmd-db.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <soc/qcom/rpmh.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <soc/qcom/tcs.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <dt-bindings/clock/qcom,rpmh.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define CLK_RPMH_ARC_EN_OFFSET 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define CLK_RPMH_VRM_EN_OFFSET 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) * struct bcm_db - Auxiliary data pertaining to each Bus Clock Manager(BCM)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) * @unit: divisor used to convert Hz value to an RPMh msg
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) * @width: multiplier used to convert Hz value to an RPMh msg
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) * @vcd: virtual clock domain that this bcm belongs to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) * @reserved: reserved to pad the struct
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) struct bcm_db {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) __le32 unit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) __le16 width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) u8 vcd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) u8 reserved;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) * struct clk_rpmh - individual rpmh clock data structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) * @hw: handle between common and hardware-specific interfaces
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) * @res_name: resource name for the rpmh clock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) * @div: clock divider to compute the clock rate
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) * @res_addr: base address of the rpmh resource within the RPMh
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) * @res_on_val: rpmh clock enable value
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) * @state: rpmh clock requested state
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) * @aggr_state: rpmh clock aggregated state
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) * @last_sent_aggr_state: rpmh clock last aggr state sent to RPMh
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) * @valid_state_mask: mask to determine the state of the rpmh clock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) * @unit: divisor to convert rate to rpmh msg in magnitudes of Khz
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) * @dev: device to which it is attached
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) * @peer: pointer to the clock rpmh sibling
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) struct clk_rpmh {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) struct clk_hw hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) const char *res_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) u8 div;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) u32 res_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) u32 res_on_val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) u32 state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) u32 aggr_state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) u32 last_sent_aggr_state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) u32 valid_state_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) u32 unit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) struct clk_rpmh *peer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) struct clk_rpmh_desc {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) struct clk_hw **clks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) size_t num_clks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) static DEFINE_MUTEX(rpmh_clk_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define __DEFINE_CLK_RPMH(_platform, _name, _name_active, _res_name, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) _res_en_offset, _res_on, _div) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) static struct clk_rpmh _platform##_##_name_active; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) static struct clk_rpmh _platform##_##_name = { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) .res_name = _res_name, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) .res_addr = _res_en_offset, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) .res_on_val = _res_on, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) .div = _div, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) .peer = &_platform##_##_name_active, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) .valid_state_mask = (BIT(RPMH_WAKE_ONLY_STATE) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) BIT(RPMH_ACTIVE_ONLY_STATE) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) BIT(RPMH_SLEEP_STATE)), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) .hw.init = &(struct clk_init_data){ \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) .ops = &clk_rpmh_ops, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) .name = #_name, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) .parent_data = &(const struct clk_parent_data){ \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) .fw_name = "xo", \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) .name = "xo_board", \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) }, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) .num_parents = 1, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) }, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) }; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) static struct clk_rpmh _platform##_##_name_active = { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) .res_name = _res_name, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) .res_addr = _res_en_offset, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) .res_on_val = _res_on, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) .div = _div, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) .peer = &_platform##_##_name, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) .valid_state_mask = (BIT(RPMH_WAKE_ONLY_STATE) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) BIT(RPMH_ACTIVE_ONLY_STATE)), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) .hw.init = &(struct clk_init_data){ \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) .ops = &clk_rpmh_ops, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) .name = #_name_active, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) .parent_data = &(const struct clk_parent_data){ \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) .fw_name = "xo", \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) .name = "xo_board", \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) }, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) .num_parents = 1, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) }, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define DEFINE_CLK_RPMH_ARC(_platform, _name, _name_active, _res_name, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) _res_on, _div) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) __DEFINE_CLK_RPMH(_platform, _name, _name_active, _res_name, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) CLK_RPMH_ARC_EN_OFFSET, _res_on, _div)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define DEFINE_CLK_RPMH_VRM(_platform, _name, _name_active, _res_name, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) _div) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) __DEFINE_CLK_RPMH(_platform, _name, _name_active, _res_name, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) CLK_RPMH_VRM_EN_OFFSET, 1, _div)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define DEFINE_CLK_RPMH_BCM(_platform, _name, _res_name) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) static struct clk_rpmh _platform##_##_name = { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) .res_name = _res_name, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) .valid_state_mask = BIT(RPMH_ACTIVE_ONLY_STATE), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) .div = 1, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) .hw.init = &(struct clk_init_data){ \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) .ops = &clk_rpmh_bcm_ops, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) .name = #_name, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) }, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) static inline struct clk_rpmh *to_clk_rpmh(struct clk_hw *_hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) return container_of(_hw, struct clk_rpmh, hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) static inline bool has_state_changed(struct clk_rpmh *c, u32 state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) return (c->last_sent_aggr_state & BIT(state))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) != (c->aggr_state & BIT(state));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) static int clk_rpmh_send(struct clk_rpmh *c, enum rpmh_state state,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) struct tcs_cmd *cmd, bool wait)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) if (wait)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) return rpmh_write(c->dev, state, cmd, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) return rpmh_write_async(c->dev, state, cmd, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) static int clk_rpmh_send_aggregate_command(struct clk_rpmh *c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) struct tcs_cmd cmd = { 0 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) u32 cmd_state, on_val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) enum rpmh_state state = RPMH_SLEEP_STATE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) bool wait;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) cmd.addr = c->res_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) cmd_state = c->aggr_state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) on_val = c->res_on_val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) for (; state <= RPMH_ACTIVE_ONLY_STATE; state++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) if (has_state_changed(c, state)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) if (cmd_state & BIT(state))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) cmd.data = on_val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) wait = cmd_state && state == RPMH_ACTIVE_ONLY_STATE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) ret = clk_rpmh_send(c, state, &cmd, wait);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) dev_err(c->dev, "set %s state of %s failed: (%d)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) !state ? "sleep" :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) state == RPMH_WAKE_ONLY_STATE ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) "wake" : "active", c->res_name, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) c->last_sent_aggr_state = c->aggr_state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) c->peer->last_sent_aggr_state = c->last_sent_aggr_state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) * Update state and aggregate state values based on enable value.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) static int clk_rpmh_aggregate_state_send_command(struct clk_rpmh *c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) bool enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) /* Nothing required to be done if already off or on */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) if (enable == c->state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) c->state = enable ? c->valid_state_mask : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) c->aggr_state = c->state | c->peer->state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) c->peer->aggr_state = c->aggr_state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) ret = clk_rpmh_send_aggregate_command(c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) if (!ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) if (ret && enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) c->state = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) else if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) c->state = c->valid_state_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) WARN(1, "clk: %s failed to %s\n", c->res_name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) enable ? "enable" : "disable");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) static int clk_rpmh_prepare(struct clk_hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) struct clk_rpmh *c = to_clk_rpmh(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) mutex_lock(&rpmh_clk_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) ret = clk_rpmh_aggregate_state_send_command(c, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) mutex_unlock(&rpmh_clk_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) static void clk_rpmh_unprepare(struct clk_hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) struct clk_rpmh *c = to_clk_rpmh(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) mutex_lock(&rpmh_clk_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) clk_rpmh_aggregate_state_send_command(c, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) mutex_unlock(&rpmh_clk_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) static unsigned long clk_rpmh_recalc_rate(struct clk_hw *hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) unsigned long prate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) struct clk_rpmh *r = to_clk_rpmh(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) * RPMh clocks have a fixed rate. Return static rate.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) return prate / r->div;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) static const struct clk_ops clk_rpmh_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) .prepare = clk_rpmh_prepare,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) .unprepare = clk_rpmh_unprepare,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) .recalc_rate = clk_rpmh_recalc_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) static int clk_rpmh_bcm_send_cmd(struct clk_rpmh *c, bool enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) struct tcs_cmd cmd = { 0 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) u32 cmd_state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) mutex_lock(&rpmh_clk_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) if (enable) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) cmd_state = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) if (c->aggr_state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) cmd_state = c->aggr_state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) cmd_state = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) if (c->last_sent_aggr_state != cmd_state) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) cmd.addr = c->res_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) cmd.data = BCM_TCS_CMD(1, enable, 0, cmd_state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) ret = clk_rpmh_send(c, RPMH_ACTIVE_ONLY_STATE, &cmd, enable);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) dev_err(c->dev, "set active state of %s failed: (%d)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) c->res_name, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) c->last_sent_aggr_state = cmd_state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) mutex_unlock(&rpmh_clk_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) static int clk_rpmh_bcm_prepare(struct clk_hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) struct clk_rpmh *c = to_clk_rpmh(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) return clk_rpmh_bcm_send_cmd(c, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) static void clk_rpmh_bcm_unprepare(struct clk_hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) struct clk_rpmh *c = to_clk_rpmh(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) clk_rpmh_bcm_send_cmd(c, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) static int clk_rpmh_bcm_set_rate(struct clk_hw *hw, unsigned long rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) unsigned long parent_rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) struct clk_rpmh *c = to_clk_rpmh(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) c->aggr_state = rate / c->unit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) * Since any non-zero value sent to hw would result in enabling the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) * clock, only send the value if the clock has already been prepared.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) if (clk_hw_is_prepared(hw))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) clk_rpmh_bcm_send_cmd(c, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) static long clk_rpmh_round_rate(struct clk_hw *hw, unsigned long rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) unsigned long *parent_rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) return rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) static unsigned long clk_rpmh_bcm_recalc_rate(struct clk_hw *hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) unsigned long prate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) struct clk_rpmh *c = to_clk_rpmh(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) return c->aggr_state * c->unit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) static const struct clk_ops clk_rpmh_bcm_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) .prepare = clk_rpmh_bcm_prepare,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) .unprepare = clk_rpmh_bcm_unprepare,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) .set_rate = clk_rpmh_bcm_set_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) .round_rate = clk_rpmh_round_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) .recalc_rate = clk_rpmh_bcm_recalc_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) /* Resource name must match resource id present in cmd-db */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) DEFINE_CLK_RPMH_ARC(sdm845, bi_tcxo, bi_tcxo_ao, "xo.lvl", 0x3, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) DEFINE_CLK_RPMH_VRM(sdm845, ln_bb_clk2, ln_bb_clk2_ao, "lnbclka2", 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) DEFINE_CLK_RPMH_VRM(sdm845, ln_bb_clk3, ln_bb_clk3_ao, "lnbclka3", 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) DEFINE_CLK_RPMH_VRM(sdm845, rf_clk1, rf_clk1_ao, "rfclka1", 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) DEFINE_CLK_RPMH_VRM(sdm845, rf_clk2, rf_clk2_ao, "rfclka2", 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) DEFINE_CLK_RPMH_VRM(sdm845, rf_clk3, rf_clk3_ao, "rfclka3", 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) DEFINE_CLK_RPMH_VRM(sm8150, rf_clk3, rf_clk3_ao, "rfclka3", 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) DEFINE_CLK_RPMH_BCM(sdm845, ipa, "IP0");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) static struct clk_hw *sdm845_rpmh_clocks[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) [RPMH_CXO_CLK] = &sdm845_bi_tcxo.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) [RPMH_CXO_CLK_A] = &sdm845_bi_tcxo_ao.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) [RPMH_LN_BB_CLK2] = &sdm845_ln_bb_clk2.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) [RPMH_LN_BB_CLK2_A] = &sdm845_ln_bb_clk2_ao.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) [RPMH_LN_BB_CLK3] = &sdm845_ln_bb_clk3.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) [RPMH_LN_BB_CLK3_A] = &sdm845_ln_bb_clk3_ao.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) [RPMH_RF_CLK1] = &sdm845_rf_clk1.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) [RPMH_RF_CLK1_A] = &sdm845_rf_clk1_ao.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) [RPMH_RF_CLK2] = &sdm845_rf_clk2.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) [RPMH_RF_CLK2_A] = &sdm845_rf_clk2_ao.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) [RPMH_RF_CLK3] = &sdm845_rf_clk3.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) [RPMH_RF_CLK3_A] = &sdm845_rf_clk3_ao.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) [RPMH_IPA_CLK] = &sdm845_ipa.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) static const struct clk_rpmh_desc clk_rpmh_sdm845 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) .clks = sdm845_rpmh_clocks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) .num_clks = ARRAY_SIZE(sdm845_rpmh_clocks),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) static struct clk_hw *sm8150_rpmh_clocks[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) [RPMH_CXO_CLK] = &sdm845_bi_tcxo.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) [RPMH_CXO_CLK_A] = &sdm845_bi_tcxo_ao.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) [RPMH_LN_BB_CLK2] = &sdm845_ln_bb_clk2.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) [RPMH_LN_BB_CLK2_A] = &sdm845_ln_bb_clk2_ao.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) [RPMH_LN_BB_CLK3] = &sdm845_ln_bb_clk3.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) [RPMH_LN_BB_CLK3_A] = &sdm845_ln_bb_clk3_ao.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) [RPMH_RF_CLK1] = &sdm845_rf_clk1.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) [RPMH_RF_CLK1_A] = &sdm845_rf_clk1_ao.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) [RPMH_RF_CLK2] = &sdm845_rf_clk2.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) [RPMH_RF_CLK2_A] = &sdm845_rf_clk2_ao.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) [RPMH_RF_CLK3] = &sdm845_rf_clk3.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) [RPMH_RF_CLK3_A] = &sdm845_rf_clk3_ao.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) static const struct clk_rpmh_desc clk_rpmh_sm8150 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) .clks = sm8150_rpmh_clocks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) .num_clks = ARRAY_SIZE(sm8150_rpmh_clocks),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) static struct clk_hw *sc7180_rpmh_clocks[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) [RPMH_CXO_CLK] = &sdm845_bi_tcxo.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) [RPMH_CXO_CLK_A] = &sdm845_bi_tcxo_ao.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) [RPMH_LN_BB_CLK2] = &sdm845_ln_bb_clk2.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) [RPMH_LN_BB_CLK2_A] = &sdm845_ln_bb_clk2_ao.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) [RPMH_LN_BB_CLK3] = &sdm845_ln_bb_clk3.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) [RPMH_LN_BB_CLK3_A] = &sdm845_ln_bb_clk3_ao.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) [RPMH_RF_CLK1] = &sdm845_rf_clk1.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) [RPMH_RF_CLK1_A] = &sdm845_rf_clk1_ao.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) [RPMH_RF_CLK2] = &sdm845_rf_clk2.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) [RPMH_RF_CLK2_A] = &sdm845_rf_clk2_ao.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) [RPMH_IPA_CLK] = &sdm845_ipa.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) static const struct clk_rpmh_desc clk_rpmh_sc7180 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) .clks = sc7180_rpmh_clocks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) .num_clks = ARRAY_SIZE(sc7180_rpmh_clocks),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) DEFINE_CLK_RPMH_VRM(sm8250, ln_bb_clk1, ln_bb_clk1_ao, "lnbclka1", 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) static struct clk_hw *sm8250_rpmh_clocks[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) [RPMH_CXO_CLK] = &sdm845_bi_tcxo.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) [RPMH_CXO_CLK_A] = &sdm845_bi_tcxo_ao.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) [RPMH_LN_BB_CLK1] = &sm8250_ln_bb_clk1.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) [RPMH_LN_BB_CLK1_A] = &sm8250_ln_bb_clk1_ao.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) [RPMH_LN_BB_CLK2] = &sdm845_ln_bb_clk2.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) [RPMH_LN_BB_CLK2_A] = &sdm845_ln_bb_clk2_ao.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) [RPMH_LN_BB_CLK3] = &sdm845_ln_bb_clk3.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) [RPMH_LN_BB_CLK3_A] = &sdm845_ln_bb_clk3_ao.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) [RPMH_RF_CLK1] = &sdm845_rf_clk1.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) [RPMH_RF_CLK1_A] = &sdm845_rf_clk1_ao.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) [RPMH_RF_CLK3] = &sdm845_rf_clk3.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) [RPMH_RF_CLK3_A] = &sdm845_rf_clk3_ao.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) static const struct clk_rpmh_desc clk_rpmh_sm8250 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) .clks = sm8250_rpmh_clocks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) .num_clks = ARRAY_SIZE(sm8250_rpmh_clocks),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) static struct clk_hw *of_clk_rpmh_hw_get(struct of_phandle_args *clkspec,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) void *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) struct clk_rpmh_desc *rpmh = data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) unsigned int idx = clkspec->args[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) if (idx >= rpmh->num_clks) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) pr_err("%s: invalid index %u\n", __func__, idx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) return ERR_PTR(-EINVAL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) return rpmh->clks[idx];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) static int clk_rpmh_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) struct clk_hw **hw_clks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) struct clk_rpmh *rpmh_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) const struct clk_rpmh_desc *desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) int ret, i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) desc = of_device_get_match_data(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) if (!desc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) hw_clks = desc->clks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) for (i = 0; i < desc->num_clks; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) const char *name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) u32 res_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) size_t aux_data_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) const struct bcm_db *data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) if (!hw_clks[i])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) name = hw_clks[i]->init->name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) rpmh_clk = to_clk_rpmh(hw_clks[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) res_addr = cmd_db_read_addr(rpmh_clk->res_name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) if (!res_addr) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) dev_err(&pdev->dev, "missing RPMh resource address for %s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) rpmh_clk->res_name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) data = cmd_db_read_aux_data(rpmh_clk->res_name, &aux_data_len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) if (IS_ERR(data)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) ret = PTR_ERR(data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) dev_err(&pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) "error reading RPMh aux data for %s (%d)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) rpmh_clk->res_name, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) /* Convert unit from Khz to Hz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) if (aux_data_len == sizeof(*data))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) rpmh_clk->unit = le32_to_cpu(data->unit) * 1000ULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) rpmh_clk->res_addr += res_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) rpmh_clk->dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) ret = devm_clk_hw_register(&pdev->dev, hw_clks[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) dev_err(&pdev->dev, "failed to register %s\n", name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) /* typecast to silence compiler warning */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) ret = devm_of_clk_add_hw_provider(&pdev->dev, of_clk_rpmh_hw_get,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) (void *)desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) dev_err(&pdev->dev, "Failed to add clock provider\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) dev_dbg(&pdev->dev, "Registered RPMh clocks\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) static const struct of_device_id clk_rpmh_match_table[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) { .compatible = "qcom,sc7180-rpmh-clk", .data = &clk_rpmh_sc7180},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) { .compatible = "qcom,sdm845-rpmh-clk", .data = &clk_rpmh_sdm845},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) { .compatible = "qcom,sm8150-rpmh-clk", .data = &clk_rpmh_sm8150},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) { .compatible = "qcom,sm8250-rpmh-clk", .data = &clk_rpmh_sm8250},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) MODULE_DEVICE_TABLE(of, clk_rpmh_match_table);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) static struct platform_driver clk_rpmh_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) .probe = clk_rpmh_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) .name = "clk-rpmh",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) .of_match_table = clk_rpmh_match_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) static int __init clk_rpmh_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) return platform_driver_register(&clk_rpmh_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) core_initcall(clk_rpmh_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) static void __exit clk_rpmh_exit(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) platform_driver_unregister(&clk_rpmh_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) module_exit(clk_rpmh_exit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) MODULE_DESCRIPTION("QCOM RPMh Clock Driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) MODULE_LICENSE("GPL v2");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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