^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (c) 2016, Linaro Limited
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Copyright (c) 2014, The Linux Foundation. All rights reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include <linux/clk-provider.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/export.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/mutex.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/mfd/qcom_rpm.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/of_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <dt-bindings/mfd/qcom-rpm.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <dt-bindings/clock/qcom,rpmcc.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define QCOM_RPM_MISC_CLK_TYPE 0x306b6c63
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define QCOM_RPM_SCALING_ENABLE_ID 0x2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define QCOM_RPM_XO_MODE_ON 0x2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define DEFINE_CLK_RPM(_platform, _name, _active, r_id) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) static struct clk_rpm _platform##_##_active; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) static struct clk_rpm _platform##_##_name = { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) .rpm_clk_id = (r_id), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) .peer = &_platform##_##_active, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) .rate = INT_MAX, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) .hw.init = &(struct clk_init_data){ \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) .ops = &clk_rpm_ops, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) .name = #_name, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) .parent_names = (const char *[]){ "pxo_board" }, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) .num_parents = 1, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) }, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) }; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) static struct clk_rpm _platform##_##_active = { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) .rpm_clk_id = (r_id), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) .peer = &_platform##_##_name, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) .active_only = true, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) .rate = INT_MAX, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) .hw.init = &(struct clk_init_data){ \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) .ops = &clk_rpm_ops, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) .name = #_active, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) .parent_names = (const char *[]){ "pxo_board" }, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) .num_parents = 1, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) }, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define DEFINE_CLK_RPM_XO_BUFFER(_platform, _name, _active, offset) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) static struct clk_rpm _platform##_##_name = { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) .rpm_clk_id = QCOM_RPM_CXO_BUFFERS, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) .xo_offset = (offset), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) .hw.init = &(struct clk_init_data){ \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) .ops = &clk_rpm_xo_ops, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) .name = #_name, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) .parent_names = (const char *[]){ "cxo_board" }, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) .num_parents = 1, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) }, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define DEFINE_CLK_RPM_FIXED(_platform, _name, _active, r_id, r) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) static struct clk_rpm _platform##_##_name = { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) .rpm_clk_id = (r_id), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) .rate = (r), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) .hw.init = &(struct clk_init_data){ \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) .ops = &clk_rpm_fixed_ops, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) .name = #_name, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) .parent_names = (const char *[]){ "pxo" }, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) .num_parents = 1, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) }, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define DEFINE_CLK_RPM_PXO_BRANCH(_platform, _name, _active, r_id, r) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) static struct clk_rpm _platform##_##_active; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) static struct clk_rpm _platform##_##_name = { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) .rpm_clk_id = (r_id), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) .active_only = true, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) .peer = &_platform##_##_active, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) .rate = (r), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) .branch = true, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) .hw.init = &(struct clk_init_data){ \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) .ops = &clk_rpm_branch_ops, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) .name = #_name, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) .parent_names = (const char *[]){ "pxo_board" }, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) .num_parents = 1, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) }, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) }; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) static struct clk_rpm _platform##_##_active = { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) .rpm_clk_id = (r_id), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) .peer = &_platform##_##_name, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) .rate = (r), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) .branch = true, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) .hw.init = &(struct clk_init_data){ \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) .ops = &clk_rpm_branch_ops, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) .name = #_active, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) .parent_names = (const char *[]){ "pxo_board" }, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) .num_parents = 1, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) }, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define DEFINE_CLK_RPM_CXO_BRANCH(_platform, _name, _active, r_id, r) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) static struct clk_rpm _platform##_##_active; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) static struct clk_rpm _platform##_##_name = { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) .rpm_clk_id = (r_id), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) .peer = &_platform##_##_active, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) .rate = (r), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) .branch = true, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) .hw.init = &(struct clk_init_data){ \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) .ops = &clk_rpm_branch_ops, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) .name = #_name, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) .parent_names = (const char *[]){ "cxo_board" }, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) .num_parents = 1, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) }, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) }; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) static struct clk_rpm _platform##_##_active = { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) .rpm_clk_id = (r_id), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) .active_only = true, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) .peer = &_platform##_##_name, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) .rate = (r), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) .branch = true, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) .hw.init = &(struct clk_init_data){ \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) .ops = &clk_rpm_branch_ops, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) .name = #_active, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) .parent_names = (const char *[]){ "cxo_board" }, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) .num_parents = 1, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) }, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define to_clk_rpm(_hw) container_of(_hw, struct clk_rpm, hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) struct rpm_cc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) struct clk_rpm {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) const int rpm_clk_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) const int xo_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) const bool active_only;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) unsigned long rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) bool enabled;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) bool branch;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) struct clk_rpm *peer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) struct clk_hw hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) struct qcom_rpm *rpm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) struct rpm_cc *rpm_cc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) struct rpm_cc {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) struct qcom_rpm *rpm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) struct clk_rpm **clks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) size_t num_clks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) u32 xo_buffer_value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) struct mutex xo_lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) struct rpm_clk_desc {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) struct clk_rpm **clks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) size_t num_clks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) static DEFINE_MUTEX(rpm_clk_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) static int clk_rpm_handoff(struct clk_rpm *r)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) u32 value = INT_MAX;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) * The vendor tree simply reads the status for this
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) * RPM clock.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) if (r->rpm_clk_id == QCOM_RPM_PLL_4 ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) r->rpm_clk_id == QCOM_RPM_CXO_BUFFERS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) ret = qcom_rpm_write(r->rpm, QCOM_RPM_ACTIVE_STATE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) r->rpm_clk_id, &value, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) ret = qcom_rpm_write(r->rpm, QCOM_RPM_SLEEP_STATE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) r->rpm_clk_id, &value, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) static int clk_rpm_set_rate_active(struct clk_rpm *r, unsigned long rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) u32 value = DIV_ROUND_UP(rate, 1000); /* to kHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) return qcom_rpm_write(r->rpm, QCOM_RPM_ACTIVE_STATE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) r->rpm_clk_id, &value, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) static int clk_rpm_set_rate_sleep(struct clk_rpm *r, unsigned long rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) u32 value = DIV_ROUND_UP(rate, 1000); /* to kHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) return qcom_rpm_write(r->rpm, QCOM_RPM_SLEEP_STATE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) r->rpm_clk_id, &value, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) static void to_active_sleep(struct clk_rpm *r, unsigned long rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) unsigned long *active, unsigned long *sleep)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) *active = rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) * Active-only clocks don't care what the rate is during sleep. So,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) * they vote for zero.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) if (r->active_only)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) *sleep = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) *sleep = *active;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) static int clk_rpm_prepare(struct clk_hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) struct clk_rpm *r = to_clk_rpm(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) struct clk_rpm *peer = r->peer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) unsigned long this_rate = 0, this_sleep_rate = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) unsigned long peer_rate = 0, peer_sleep_rate = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) unsigned long active_rate, sleep_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) mutex_lock(&rpm_clk_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) /* Don't send requests to the RPM if the rate has not been set. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) if (!r->rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) to_active_sleep(r, r->rate, &this_rate, &this_sleep_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) /* Take peer clock's rate into account only if it's enabled. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) if (peer->enabled)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) to_active_sleep(peer, peer->rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) &peer_rate, &peer_sleep_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) active_rate = max(this_rate, peer_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) if (r->branch)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) active_rate = !!active_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) ret = clk_rpm_set_rate_active(r, active_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) sleep_rate = max(this_sleep_rate, peer_sleep_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) if (r->branch)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) sleep_rate = !!sleep_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) ret = clk_rpm_set_rate_sleep(r, sleep_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) /* Undo the active set vote and restore it */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) ret = clk_rpm_set_rate_active(r, peer_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) if (!ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) r->enabled = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) mutex_unlock(&rpm_clk_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) static void clk_rpm_unprepare(struct clk_hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) struct clk_rpm *r = to_clk_rpm(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) struct clk_rpm *peer = r->peer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) unsigned long peer_rate = 0, peer_sleep_rate = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) unsigned long active_rate, sleep_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) mutex_lock(&rpm_clk_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) if (!r->rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) /* Take peer clock's rate into account only if it's enabled. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) if (peer->enabled)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) to_active_sleep(peer, peer->rate, &peer_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) &peer_sleep_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) active_rate = r->branch ? !!peer_rate : peer_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) ret = clk_rpm_set_rate_active(r, active_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) sleep_rate = r->branch ? !!peer_sleep_rate : peer_sleep_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) ret = clk_rpm_set_rate_sleep(r, sleep_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) r->enabled = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) mutex_unlock(&rpm_clk_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) static int clk_rpm_xo_prepare(struct clk_hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) struct clk_rpm *r = to_clk_rpm(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) struct rpm_cc *rcc = r->rpm_cc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) int ret, clk_id = r->rpm_clk_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) u32 value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) mutex_lock(&rcc->xo_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) value = rcc->xo_buffer_value | (QCOM_RPM_XO_MODE_ON << r->xo_offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) ret = qcom_rpm_write(r->rpm, QCOM_RPM_ACTIVE_STATE, clk_id, &value, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) if (!ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) r->enabled = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) rcc->xo_buffer_value = value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) mutex_unlock(&rcc->xo_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) static void clk_rpm_xo_unprepare(struct clk_hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) struct clk_rpm *r = to_clk_rpm(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) struct rpm_cc *rcc = r->rpm_cc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) int ret, clk_id = r->rpm_clk_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) u32 value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) mutex_lock(&rcc->xo_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) value = rcc->xo_buffer_value & ~(QCOM_RPM_XO_MODE_ON << r->xo_offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) ret = qcom_rpm_write(r->rpm, QCOM_RPM_ACTIVE_STATE, clk_id, &value, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) if (!ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) r->enabled = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) rcc->xo_buffer_value = value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) mutex_unlock(&rcc->xo_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) static int clk_rpm_fixed_prepare(struct clk_hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) struct clk_rpm *r = to_clk_rpm(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) u32 value = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) ret = qcom_rpm_write(r->rpm, QCOM_RPM_ACTIVE_STATE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) r->rpm_clk_id, &value, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) if (!ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) r->enabled = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) static void clk_rpm_fixed_unprepare(struct clk_hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) struct clk_rpm *r = to_clk_rpm(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) u32 value = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) ret = qcom_rpm_write(r->rpm, QCOM_RPM_ACTIVE_STATE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) r->rpm_clk_id, &value, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) if (!ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) r->enabled = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) static int clk_rpm_set_rate(struct clk_hw *hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) unsigned long rate, unsigned long parent_rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) struct clk_rpm *r = to_clk_rpm(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) struct clk_rpm *peer = r->peer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) unsigned long active_rate, sleep_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) unsigned long this_rate = 0, this_sleep_rate = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) unsigned long peer_rate = 0, peer_sleep_rate = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) mutex_lock(&rpm_clk_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) if (!r->enabled)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) to_active_sleep(r, rate, &this_rate, &this_sleep_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) /* Take peer clock's rate into account only if it's enabled. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) if (peer->enabled)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) to_active_sleep(peer, peer->rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) &peer_rate, &peer_sleep_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) active_rate = max(this_rate, peer_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) ret = clk_rpm_set_rate_active(r, active_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) sleep_rate = max(this_sleep_rate, peer_sleep_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) ret = clk_rpm_set_rate_sleep(r, sleep_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) r->rate = rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) mutex_unlock(&rpm_clk_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) static long clk_rpm_round_rate(struct clk_hw *hw, unsigned long rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) unsigned long *parent_rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) * RPM handles rate rounding and we don't have a way to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) * know what the rate will be, so just return whatever
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) * rate is requested.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) return rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) static unsigned long clk_rpm_recalc_rate(struct clk_hw *hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) unsigned long parent_rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) struct clk_rpm *r = to_clk_rpm(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) * RPM handles rate rounding and we don't have a way to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) * know what the rate will be, so just return whatever
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) * rate was set.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) return r->rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) static const struct clk_ops clk_rpm_xo_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) .prepare = clk_rpm_xo_prepare,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) .unprepare = clk_rpm_xo_unprepare,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) static const struct clk_ops clk_rpm_fixed_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) .prepare = clk_rpm_fixed_prepare,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) .unprepare = clk_rpm_fixed_unprepare,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) .round_rate = clk_rpm_round_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) .recalc_rate = clk_rpm_recalc_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) static const struct clk_ops clk_rpm_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) .prepare = clk_rpm_prepare,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) .unprepare = clk_rpm_unprepare,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) .set_rate = clk_rpm_set_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) .round_rate = clk_rpm_round_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) .recalc_rate = clk_rpm_recalc_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) static const struct clk_ops clk_rpm_branch_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) .prepare = clk_rpm_prepare,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) .unprepare = clk_rpm_unprepare,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) .round_rate = clk_rpm_round_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) .recalc_rate = clk_rpm_recalc_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) /* MSM8660/APQ8060 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) DEFINE_CLK_RPM(msm8660, afab_clk, afab_a_clk, QCOM_RPM_APPS_FABRIC_CLK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) DEFINE_CLK_RPM(msm8660, sfab_clk, sfab_a_clk, QCOM_RPM_SYS_FABRIC_CLK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) DEFINE_CLK_RPM(msm8660, mmfab_clk, mmfab_a_clk, QCOM_RPM_MM_FABRIC_CLK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) DEFINE_CLK_RPM(msm8660, daytona_clk, daytona_a_clk, QCOM_RPM_DAYTONA_FABRIC_CLK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) DEFINE_CLK_RPM(msm8660, sfpb_clk, sfpb_a_clk, QCOM_RPM_SFPB_CLK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) DEFINE_CLK_RPM(msm8660, cfpb_clk, cfpb_a_clk, QCOM_RPM_CFPB_CLK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) DEFINE_CLK_RPM(msm8660, mmfpb_clk, mmfpb_a_clk, QCOM_RPM_MMFPB_CLK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) DEFINE_CLK_RPM(msm8660, smi_clk, smi_a_clk, QCOM_RPM_SMI_CLK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) DEFINE_CLK_RPM(msm8660, ebi1_clk, ebi1_a_clk, QCOM_RPM_EBI1_CLK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) DEFINE_CLK_RPM_FIXED(msm8660, pll4_clk, pll4_a_clk, QCOM_RPM_PLL_4, 540672000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) static struct clk_rpm *msm8660_clks[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) [RPM_APPS_FABRIC_CLK] = &msm8660_afab_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) [RPM_APPS_FABRIC_A_CLK] = &msm8660_afab_a_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) [RPM_SYS_FABRIC_CLK] = &msm8660_sfab_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) [RPM_SYS_FABRIC_A_CLK] = &msm8660_sfab_a_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) [RPM_MM_FABRIC_CLK] = &msm8660_mmfab_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) [RPM_MM_FABRIC_A_CLK] = &msm8660_mmfab_a_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) [RPM_DAYTONA_FABRIC_CLK] = &msm8660_daytona_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) [RPM_DAYTONA_FABRIC_A_CLK] = &msm8660_daytona_a_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) [RPM_SFPB_CLK] = &msm8660_sfpb_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) [RPM_SFPB_A_CLK] = &msm8660_sfpb_a_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) [RPM_CFPB_CLK] = &msm8660_cfpb_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) [RPM_CFPB_A_CLK] = &msm8660_cfpb_a_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) [RPM_MMFPB_CLK] = &msm8660_mmfpb_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) [RPM_MMFPB_A_CLK] = &msm8660_mmfpb_a_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) [RPM_SMI_CLK] = &msm8660_smi_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) [RPM_SMI_A_CLK] = &msm8660_smi_a_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) [RPM_EBI1_CLK] = &msm8660_ebi1_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) [RPM_EBI1_A_CLK] = &msm8660_ebi1_a_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) [RPM_PLL4_CLK] = &msm8660_pll4_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) static const struct rpm_clk_desc rpm_clk_msm8660 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) .clks = msm8660_clks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) .num_clks = ARRAY_SIZE(msm8660_clks),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) /* apq8064 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) DEFINE_CLK_RPM(apq8064, afab_clk, afab_a_clk, QCOM_RPM_APPS_FABRIC_CLK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) DEFINE_CLK_RPM(apq8064, cfpb_clk, cfpb_a_clk, QCOM_RPM_CFPB_CLK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) DEFINE_CLK_RPM(apq8064, daytona_clk, daytona_a_clk, QCOM_RPM_DAYTONA_FABRIC_CLK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) DEFINE_CLK_RPM(apq8064, ebi1_clk, ebi1_a_clk, QCOM_RPM_EBI1_CLK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) DEFINE_CLK_RPM(apq8064, mmfab_clk, mmfab_a_clk, QCOM_RPM_MM_FABRIC_CLK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) DEFINE_CLK_RPM(apq8064, mmfpb_clk, mmfpb_a_clk, QCOM_RPM_MMFPB_CLK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) DEFINE_CLK_RPM(apq8064, sfab_clk, sfab_a_clk, QCOM_RPM_SYS_FABRIC_CLK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) DEFINE_CLK_RPM(apq8064, sfpb_clk, sfpb_a_clk, QCOM_RPM_SFPB_CLK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) DEFINE_CLK_RPM(apq8064, qdss_clk, qdss_a_clk, QCOM_RPM_QDSS_CLK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) DEFINE_CLK_RPM_XO_BUFFER(apq8064, xo_d0_clk, xo_d0_a_clk, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) DEFINE_CLK_RPM_XO_BUFFER(apq8064, xo_d1_clk, xo_d1_a_clk, 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) DEFINE_CLK_RPM_XO_BUFFER(apq8064, xo_a0_clk, xo_a0_a_clk, 16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) DEFINE_CLK_RPM_XO_BUFFER(apq8064, xo_a1_clk, xo_a1_a_clk, 24);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) DEFINE_CLK_RPM_XO_BUFFER(apq8064, xo_a2_clk, xo_a2_a_clk, 28);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) static struct clk_rpm *apq8064_clks[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) [RPM_APPS_FABRIC_CLK] = &apq8064_afab_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) [RPM_APPS_FABRIC_A_CLK] = &apq8064_afab_a_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) [RPM_CFPB_CLK] = &apq8064_cfpb_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) [RPM_CFPB_A_CLK] = &apq8064_cfpb_a_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) [RPM_DAYTONA_FABRIC_CLK] = &apq8064_daytona_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) [RPM_DAYTONA_FABRIC_A_CLK] = &apq8064_daytona_a_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) [RPM_EBI1_CLK] = &apq8064_ebi1_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) [RPM_EBI1_A_CLK] = &apq8064_ebi1_a_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) [RPM_MM_FABRIC_CLK] = &apq8064_mmfab_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) [RPM_MM_FABRIC_A_CLK] = &apq8064_mmfab_a_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) [RPM_MMFPB_CLK] = &apq8064_mmfpb_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) [RPM_MMFPB_A_CLK] = &apq8064_mmfpb_a_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) [RPM_SYS_FABRIC_CLK] = &apq8064_sfab_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) [RPM_SYS_FABRIC_A_CLK] = &apq8064_sfab_a_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) [RPM_SFPB_CLK] = &apq8064_sfpb_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) [RPM_SFPB_A_CLK] = &apq8064_sfpb_a_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) [RPM_QDSS_CLK] = &apq8064_qdss_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) [RPM_QDSS_A_CLK] = &apq8064_qdss_a_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) [RPM_XO_D0] = &apq8064_xo_d0_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) [RPM_XO_D1] = &apq8064_xo_d1_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) [RPM_XO_A0] = &apq8064_xo_a0_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) [RPM_XO_A1] = &apq8064_xo_a1_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) [RPM_XO_A2] = &apq8064_xo_a2_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) static const struct rpm_clk_desc rpm_clk_apq8064 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) .clks = apq8064_clks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) .num_clks = ARRAY_SIZE(apq8064_clks),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) /* ipq806x */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) DEFINE_CLK_RPM(ipq806x, afab_clk, afab_a_clk, QCOM_RPM_APPS_FABRIC_CLK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) DEFINE_CLK_RPM(ipq806x, cfpb_clk, cfpb_a_clk, QCOM_RPM_CFPB_CLK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) DEFINE_CLK_RPM(ipq806x, daytona_clk, daytona_a_clk, QCOM_RPM_DAYTONA_FABRIC_CLK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) DEFINE_CLK_RPM(ipq806x, ebi1_clk, ebi1_a_clk, QCOM_RPM_EBI1_CLK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) DEFINE_CLK_RPM(ipq806x, sfab_clk, sfab_a_clk, QCOM_RPM_SYS_FABRIC_CLK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) DEFINE_CLK_RPM(ipq806x, sfpb_clk, sfpb_a_clk, QCOM_RPM_SFPB_CLK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) DEFINE_CLK_RPM(ipq806x, nss_fabric_0_clk, nss_fabric_0_a_clk, QCOM_RPM_NSS_FABRIC_0_CLK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) DEFINE_CLK_RPM(ipq806x, nss_fabric_1_clk, nss_fabric_1_a_clk, QCOM_RPM_NSS_FABRIC_1_CLK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) static struct clk_rpm *ipq806x_clks[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) [RPM_APPS_FABRIC_CLK] = &ipq806x_afab_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) [RPM_APPS_FABRIC_A_CLK] = &ipq806x_afab_a_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) [RPM_CFPB_CLK] = &ipq806x_cfpb_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) [RPM_CFPB_A_CLK] = &ipq806x_cfpb_a_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) [RPM_DAYTONA_FABRIC_CLK] = &ipq806x_daytona_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) [RPM_DAYTONA_FABRIC_A_CLK] = &ipq806x_daytona_a_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) [RPM_EBI1_CLK] = &ipq806x_ebi1_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) [RPM_EBI1_A_CLK] = &ipq806x_ebi1_a_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) [RPM_SYS_FABRIC_CLK] = &ipq806x_sfab_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) [RPM_SYS_FABRIC_A_CLK] = &ipq806x_sfab_a_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) [RPM_SFPB_CLK] = &ipq806x_sfpb_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) [RPM_SFPB_A_CLK] = &ipq806x_sfpb_a_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) [RPM_NSS_FABRIC_0_CLK] = &ipq806x_nss_fabric_0_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) [RPM_NSS_FABRIC_0_A_CLK] = &ipq806x_nss_fabric_0_a_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) [RPM_NSS_FABRIC_1_CLK] = &ipq806x_nss_fabric_1_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) [RPM_NSS_FABRIC_1_A_CLK] = &ipq806x_nss_fabric_1_a_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) static const struct rpm_clk_desc rpm_clk_ipq806x = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) .clks = ipq806x_clks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) .num_clks = ARRAY_SIZE(ipq806x_clks),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) static const struct of_device_id rpm_clk_match_table[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) { .compatible = "qcom,rpmcc-msm8660", .data = &rpm_clk_msm8660 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) { .compatible = "qcom,rpmcc-apq8060", .data = &rpm_clk_msm8660 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) { .compatible = "qcom,rpmcc-apq8064", .data = &rpm_clk_apq8064 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) { .compatible = "qcom,rpmcc-ipq806x", .data = &rpm_clk_ipq806x },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) MODULE_DEVICE_TABLE(of, rpm_clk_match_table);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) static struct clk_hw *qcom_rpm_clk_hw_get(struct of_phandle_args *clkspec,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) void *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) struct rpm_cc *rcc = data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) unsigned int idx = clkspec->args[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) if (idx >= rcc->num_clks) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) pr_err("%s: invalid index %u\n", __func__, idx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) return ERR_PTR(-EINVAL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) return rcc->clks[idx] ? &rcc->clks[idx]->hw : ERR_PTR(-ENOENT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) static int rpm_clk_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) struct rpm_cc *rcc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) size_t num_clks, i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) struct qcom_rpm *rpm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) struct clk_rpm **rpm_clks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) const struct rpm_clk_desc *desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) rpm = dev_get_drvdata(pdev->dev.parent);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) if (!rpm) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) dev_err(&pdev->dev, "Unable to retrieve handle to RPM\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) desc = of_device_get_match_data(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) if (!desc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) rpm_clks = desc->clks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) num_clks = desc->num_clks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) rcc = devm_kzalloc(&pdev->dev, sizeof(*rcc), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) if (!rcc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) rcc->clks = rpm_clks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) rcc->num_clks = num_clks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) mutex_init(&rcc->xo_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) for (i = 0; i < num_clks; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) if (!rpm_clks[i])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) rpm_clks[i]->rpm = rpm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) rpm_clks[i]->rpm_cc = rcc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) ret = clk_rpm_handoff(rpm_clks[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) for (i = 0; i < num_clks; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) if (!rpm_clks[i])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) ret = devm_clk_hw_register(&pdev->dev, &rpm_clks[i]->hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) ret = of_clk_add_hw_provider(pdev->dev.of_node, qcom_rpm_clk_hw_get,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) rcc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) err:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) dev_err(&pdev->dev, "Error registering RPM Clock driver (%d)\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) static int rpm_clk_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) of_clk_del_provider(pdev->dev.of_node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) static struct platform_driver rpm_clk_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) .name = "qcom-clk-rpm",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) .of_match_table = rpm_clk_match_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) .probe = rpm_clk_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) .remove = rpm_clk_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) static int __init rpm_clk_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) return platform_driver_register(&rpm_clk_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) core_initcall(rpm_clk_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) static void __exit rpm_clk_exit(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) platform_driver_unregister(&rpm_clk_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) module_exit(rpm_clk_exit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) MODULE_DESCRIPTION("Qualcomm RPM Clock Controller Driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) MODULE_LICENSE("GPL v2");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) MODULE_ALIAS("platform:qcom-clk-rpm");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
3 Commits
0 Branches
0 Tags