Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3)  * Copyright (c) 2014, The Linux Foundation. All rights reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7) #include <linux/bitops.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8) #include <linux/regmap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9) #include <linux/export.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include "clk-regmap-mux.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) static inline struct clk_regmap_mux *to_clk_regmap_mux(struct clk_hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) 	return container_of(to_clk_regmap(hw), struct clk_regmap_mux, clkr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) static u8 mux_get_parent(struct clk_hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) 	struct clk_regmap_mux *mux = to_clk_regmap_mux(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) 	struct clk_regmap *clkr = to_clk_regmap(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) 	unsigned int mask = GENMASK(mux->width - 1, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) 	unsigned int val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) 	regmap_read(clkr->regmap, mux->reg, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) 	val >>= mux->shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) 	val &= mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) 	if (mux->parent_map)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) 		return qcom_find_cfg_index(hw, mux->parent_map, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) 	return val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) static int mux_set_parent(struct clk_hw *hw, u8 index)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) 	struct clk_regmap_mux *mux = to_clk_regmap_mux(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) 	struct clk_regmap *clkr = to_clk_regmap(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) 	unsigned int mask = GENMASK(mux->width + mux->shift - 1, mux->shift);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) 	unsigned int val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) 	if (mux->parent_map)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) 		index = mux->parent_map[index].cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) 	val = index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) 	val <<= mux->shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) 	return regmap_update_bits(clkr->regmap, mux->reg, mask, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) const struct clk_ops clk_regmap_mux_closest_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) 	.get_parent = mux_get_parent,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) 	.set_parent = mux_set_parent,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) 	.determine_rate = __clk_mux_determine_rate_closest,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) EXPORT_SYMBOL_GPL(clk_regmap_mux_closest_ops);