Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) /* SPDX-License-Identifier: GPL-2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3)  * Copyright (c) 2017, Linaro Limited
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4)  * Author: Georgi Djakov <georgi.djakov@linaro.org>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7) #ifndef __QCOM_CLK_REGMAP_MUX_DIV_H__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8) #define __QCOM_CLK_REGMAP_MUX_DIV_H__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/clk-provider.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include "clk-regmap.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)  * struct mux_div_clk - combined mux/divider clock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)  * @reg_offset: offset of the mux/divider register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)  * @hid_width:	number of bits in half integer divider
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)  * @hid_shift:	lowest bit of hid value field
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)  * @src_width:	number of bits in source select
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)  * @src_shift:	lowest bit of source select field
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)  * @div:	the divider raw configuration value
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)  * @src:	the mux index which will be used if the clock is enabled
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)  * @parent_map: map from parent_names index to src_sel field
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)  * @clkr:	handle between common and hardware-specific interfaces
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)  * @pclk:	the input PLL clock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)  * @clk_nb:	clock notifier for rate changes of the input PLL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) struct clk_regmap_mux_div {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) 	u32				reg_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) 	u32				hid_width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) 	u32				hid_shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) 	u32				src_width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) 	u32				src_shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) 	u32				div;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) 	u32				src;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) 	const u32			*parent_map;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) 	struct clk_regmap		clkr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) 	struct clk			*pclk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) 	struct notifier_block		clk_nb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) extern const struct clk_ops clk_regmap_mux_div_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) extern int mux_div_set_src_div(struct clk_regmap_mux_div *md, u32 src, u32 div);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #endif