^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /* Copyright (c) 2013, 2018, The Linux Foundation. All rights reserved. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) #ifndef __QCOM_CLK_RCG_H__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) #define __QCOM_CLK_RCG_H__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include <linux/clk-provider.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include "clk-regmap.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #define F(f, s, h, m, n) { (f), (s), (2 * (h) - 1), (m), (n) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) struct freq_tbl {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) unsigned long freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) u8 src;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) u8 pre_div;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) u16 m;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) u16 n;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) * struct mn - M/N:D counter
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) * @mnctr_en_bit: bit to enable mn counter
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) * @mnctr_reset_bit: bit to assert mn counter reset
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) * @mnctr_mode_shift: lowest bit of mn counter mode field
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) * @n_val_shift: lowest bit of n value field
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) * @m_val_shift: lowest bit of m value field
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) * @width: number of bits in m/n/d values
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) * @reset_in_cc: true if the mnctr_reset_bit is in the CC register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) struct mn {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) u8 mnctr_en_bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) u8 mnctr_reset_bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) u8 mnctr_mode_shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define MNCTR_MODE_DUAL 0x2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define MNCTR_MODE_MASK 0x3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) u8 n_val_shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) u8 m_val_shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) u8 width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) bool reset_in_cc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) * struct pre_div - pre-divider
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) * @pre_div_shift: lowest bit of pre divider field
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) * @pre_div_width: number of bits in predivider
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) struct pre_div {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) u8 pre_div_shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) u8 pre_div_width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) * struct src_sel - source selector
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) * @src_sel_shift: lowest bit of source selection field
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) * @parent_map: map from software's parent index to hardware's src_sel field
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) struct src_sel {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) u8 src_sel_shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define SRC_SEL_MASK 0x7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) const struct parent_map *parent_map;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) * struct clk_rcg - root clock generator
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) * @ns_reg: NS register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) * @md_reg: MD register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) * @mn: mn counter
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) * @p: pre divider
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) * @s: source selector
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) * @freq_tbl: frequency table
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) * @clkr: regmap clock handle
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) * @lock: register lock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) struct clk_rcg {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) u32 ns_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) u32 md_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) struct mn mn;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) struct pre_div p;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) struct src_sel s;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) const struct freq_tbl *freq_tbl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) struct clk_regmap clkr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) extern const struct clk_ops clk_rcg_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) extern const struct clk_ops clk_rcg_bypass_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) extern const struct clk_ops clk_rcg_bypass2_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) extern const struct clk_ops clk_rcg_pixel_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) extern const struct clk_ops clk_rcg_esc_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) extern const struct clk_ops clk_rcg_lcc_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define to_clk_rcg(_hw) container_of(to_clk_regmap(_hw), struct clk_rcg, clkr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) * struct clk_dyn_rcg - root clock generator with glitch free mux
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) * @mux_sel_bit: bit to switch glitch free mux
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) * @ns_reg: NS0 and NS1 register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) * @md_reg: MD0 and MD1 register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) * @bank_reg: register to XOR @mux_sel_bit into to switch glitch free mux
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) * @mn: mn counter (banked)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) * @s: source selector (banked)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) * @freq_tbl: frequency table
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) * @clkr: regmap clock handle
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) * @lock: register lock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) struct clk_dyn_rcg {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) u32 ns_reg[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) u32 md_reg[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) u32 bank_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) u8 mux_sel_bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) struct mn mn[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) struct pre_div p[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) struct src_sel s[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) const struct freq_tbl *freq_tbl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) struct clk_regmap clkr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) extern const struct clk_ops clk_dyn_rcg_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define to_clk_dyn_rcg(_hw) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) container_of(to_clk_regmap(_hw), struct clk_dyn_rcg, clkr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) * struct clk_rcg2 - root clock generator
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) * @cmd_rcgr: corresponds to *_CMD_RCGR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) * @mnd_width: number of bits in m/n/d values
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) * @hid_width: number of bits in half integer divider
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) * @safe_src_index: safe src index value
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) * @parent_map: map from software's parent index to hardware's src_sel field
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) * @freq_tbl: frequency table
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) * @clkr: regmap clock handle
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) * @cfg_off: defines the cfg register offset from the CMD_RCGR + CFG_REG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) struct clk_rcg2 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) u32 cmd_rcgr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) u8 mnd_width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) u8 hid_width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) u8 safe_src_index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) const struct parent_map *parent_map;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) const struct freq_tbl *freq_tbl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) struct clk_regmap clkr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) u8 cfg_off;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) #define to_clk_rcg2(_hw) container_of(to_clk_regmap(_hw), struct clk_rcg2, clkr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) extern const struct clk_ops clk_rcg2_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) extern const struct clk_ops clk_rcg2_floor_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) extern const struct clk_ops clk_edp_pixel_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) extern const struct clk_ops clk_byte_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) extern const struct clk_ops clk_byte2_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) extern const struct clk_ops clk_pixel_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) extern const struct clk_ops clk_gfx3d_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) extern const struct clk_ops clk_rcg2_shared_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) extern const struct clk_ops clk_dp_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) struct clk_rcg_dfs_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) struct clk_rcg2 *rcg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) struct clk_init_data *init;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) #define DEFINE_RCG_DFS(r) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) { .rcg = &r, .init = &r##_init }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) extern int qcom_cc_register_rcg_dfs(struct regmap *regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) const struct clk_rcg_dfs_data *rcgs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) size_t len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) #endif
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
3 Commits
0 Branches
0 Tags