^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (c) 2013, The Linux Foundation. All rights reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include <linux/bitops.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/export.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/clk-provider.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/regmap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <asm/div64.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include "clk-rcg.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include "common.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) static u32 ns_to_src(struct src_sel *s, u32 ns)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) ns >>= s->src_sel_shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) ns &= SRC_SEL_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) return ns;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) static u32 src_to_ns(struct src_sel *s, u8 src, u32 ns)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) u32 mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) mask = SRC_SEL_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) mask <<= s->src_sel_shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) ns &= ~mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) ns |= src << s->src_sel_shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) return ns;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) static u8 clk_rcg_get_parent(struct clk_hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) struct clk_rcg *rcg = to_clk_rcg(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) int num_parents = clk_hw_get_num_parents(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) u32 ns;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) int i, ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) ret = regmap_read(rcg->clkr.regmap, rcg->ns_reg, &ns);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) ns = ns_to_src(&rcg->s, ns);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) for (i = 0; i < num_parents; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) if (ns == rcg->s.parent_map[i].cfg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) return i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) err:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) pr_debug("%s: Clock %s has invalid parent, using default.\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) __func__, clk_hw_get_name(hw));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) static int reg_to_bank(struct clk_dyn_rcg *rcg, u32 bank)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) bank &= BIT(rcg->mux_sel_bit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) return !!bank;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) static u8 clk_dyn_rcg_get_parent(struct clk_hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) struct clk_dyn_rcg *rcg = to_clk_dyn_rcg(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) int num_parents = clk_hw_get_num_parents(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) u32 ns, reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) int bank;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) int i, ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) struct src_sel *s;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) ret = regmap_read(rcg->clkr.regmap, rcg->bank_reg, ®);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) bank = reg_to_bank(rcg, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) s = &rcg->s[bank];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) ret = regmap_read(rcg->clkr.regmap, rcg->ns_reg[bank], &ns);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) ns = ns_to_src(s, ns);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) for (i = 0; i < num_parents; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) if (ns == s->parent_map[i].cfg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) return i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) err:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) pr_debug("%s: Clock %s has invalid parent, using default.\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) __func__, clk_hw_get_name(hw));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) static int clk_rcg_set_parent(struct clk_hw *hw, u8 index)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) struct clk_rcg *rcg = to_clk_rcg(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) u32 ns;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) regmap_read(rcg->clkr.regmap, rcg->ns_reg, &ns);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) ns = src_to_ns(&rcg->s, rcg->s.parent_map[index].cfg, ns);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) regmap_write(rcg->clkr.regmap, rcg->ns_reg, ns);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) static u32 md_to_m(struct mn *mn, u32 md)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) md >>= mn->m_val_shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) md &= BIT(mn->width) - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) return md;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) static u32 ns_to_pre_div(struct pre_div *p, u32 ns)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) ns >>= p->pre_div_shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) ns &= BIT(p->pre_div_width) - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) return ns;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) static u32 pre_div_to_ns(struct pre_div *p, u8 pre_div, u32 ns)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) u32 mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) mask = BIT(p->pre_div_width) - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) mask <<= p->pre_div_shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) ns &= ~mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) ns |= pre_div << p->pre_div_shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) return ns;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) static u32 mn_to_md(struct mn *mn, u32 m, u32 n, u32 md)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) u32 mask, mask_w;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) mask_w = BIT(mn->width) - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) mask = (mask_w << mn->m_val_shift) | mask_w;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) md &= ~mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) if (n) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) m <<= mn->m_val_shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) md |= m;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) md |= ~n & mask_w;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) return md;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) static u32 ns_m_to_n(struct mn *mn, u32 ns, u32 m)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) ns = ~ns >> mn->n_val_shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) ns &= BIT(mn->width) - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) return ns + m;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) static u32 reg_to_mnctr_mode(struct mn *mn, u32 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) val >>= mn->mnctr_mode_shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) val &= MNCTR_MODE_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) return val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) static u32 mn_to_ns(struct mn *mn, u32 m, u32 n, u32 ns)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) u32 mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) mask = BIT(mn->width) - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) mask <<= mn->n_val_shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) ns &= ~mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) if (n) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) n = n - m;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) n = ~n;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) n &= BIT(mn->width) - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) n <<= mn->n_val_shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) ns |= n;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) return ns;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) static u32 mn_to_reg(struct mn *mn, u32 m, u32 n, u32 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) u32 mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) mask = MNCTR_MODE_MASK << mn->mnctr_mode_shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) mask |= BIT(mn->mnctr_en_bit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) val &= ~mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) if (n) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) val |= BIT(mn->mnctr_en_bit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) val |= MNCTR_MODE_DUAL << mn->mnctr_mode_shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) return val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) static int configure_bank(struct clk_dyn_rcg *rcg, const struct freq_tbl *f)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) u32 ns, md, reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) int bank, new_bank, ret, index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) struct mn *mn;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) struct pre_div *p;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) struct src_sel *s;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) bool enabled;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) u32 md_reg, ns_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) bool banked_mn = !!rcg->mn[1].width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) bool banked_p = !!rcg->p[1].pre_div_width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) struct clk_hw *hw = &rcg->clkr.hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) enabled = __clk_is_enabled(hw->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) ret = regmap_read(rcg->clkr.regmap, rcg->bank_reg, ®);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) bank = reg_to_bank(rcg, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) new_bank = enabled ? !bank : bank;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) ns_reg = rcg->ns_reg[new_bank];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) ret = regmap_read(rcg->clkr.regmap, ns_reg, &ns);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) if (banked_mn) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) mn = &rcg->mn[new_bank];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) md_reg = rcg->md_reg[new_bank];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) ns |= BIT(mn->mnctr_reset_bit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) ret = regmap_write(rcg->clkr.regmap, ns_reg, ns);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) ret = regmap_read(rcg->clkr.regmap, md_reg, &md);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) md = mn_to_md(mn, f->m, f->n, md);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) ret = regmap_write(rcg->clkr.regmap, md_reg, md);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) ns = mn_to_ns(mn, f->m, f->n, ns);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) ret = regmap_write(rcg->clkr.regmap, ns_reg, ns);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) /* Two NS registers means mode control is in NS register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) if (rcg->ns_reg[0] != rcg->ns_reg[1]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) ns = mn_to_reg(mn, f->m, f->n, ns);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) ret = regmap_write(rcg->clkr.regmap, ns_reg, ns);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) reg = mn_to_reg(mn, f->m, f->n, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) ret = regmap_write(rcg->clkr.regmap, rcg->bank_reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) ns &= ~BIT(mn->mnctr_reset_bit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) ret = regmap_write(rcg->clkr.regmap, ns_reg, ns);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) if (banked_p) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) p = &rcg->p[new_bank];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) ns = pre_div_to_ns(p, f->pre_div - 1, ns);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) s = &rcg->s[new_bank];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) index = qcom_find_src_index(hw, s->parent_map, f->src);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) if (index < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) return index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) ns = src_to_ns(s, s->parent_map[index].cfg, ns);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) ret = regmap_write(rcg->clkr.regmap, ns_reg, ns);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) if (enabled) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) ret = regmap_read(rcg->clkr.regmap, rcg->bank_reg, ®);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) reg ^= BIT(rcg->mux_sel_bit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) ret = regmap_write(rcg->clkr.regmap, rcg->bank_reg, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) static int clk_dyn_rcg_set_parent(struct clk_hw *hw, u8 index)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) struct clk_dyn_rcg *rcg = to_clk_dyn_rcg(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) u32 ns, md, reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) int bank;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) struct freq_tbl f = { 0 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) bool banked_mn = !!rcg->mn[1].width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) bool banked_p = !!rcg->p[1].pre_div_width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) regmap_read(rcg->clkr.regmap, rcg->bank_reg, ®);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) bank = reg_to_bank(rcg, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) regmap_read(rcg->clkr.regmap, rcg->ns_reg[bank], &ns);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) if (banked_mn) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) regmap_read(rcg->clkr.regmap, rcg->md_reg[bank], &md);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) f.m = md_to_m(&rcg->mn[bank], md);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) f.n = ns_m_to_n(&rcg->mn[bank], ns, f.m);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) if (banked_p)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) f.pre_div = ns_to_pre_div(&rcg->p[bank], ns) + 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) f.src = qcom_find_src_index(hw, rcg->s[bank].parent_map, index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) return configure_bank(rcg, &f);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) * Calculate m/n:d rate
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) * parent_rate m
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) * rate = ----------- x ---
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) * pre_div n
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) static unsigned long
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) calc_rate(unsigned long rate, u32 m, u32 n, u32 mode, u32 pre_div)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) if (pre_div)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) rate /= pre_div + 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) if (mode) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) u64 tmp = rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) tmp *= m;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) do_div(tmp, n);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) rate = tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) return rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) static unsigned long
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) clk_rcg_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) struct clk_rcg *rcg = to_clk_rcg(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) u32 pre_div, m = 0, n = 0, ns, md, mode = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) struct mn *mn = &rcg->mn;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) regmap_read(rcg->clkr.regmap, rcg->ns_reg, &ns);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) pre_div = ns_to_pre_div(&rcg->p, ns);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) if (rcg->mn.width) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) regmap_read(rcg->clkr.regmap, rcg->md_reg, &md);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) m = md_to_m(mn, md);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) n = ns_m_to_n(mn, ns, m);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) /* MN counter mode is in hw.enable_reg sometimes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) if (rcg->clkr.enable_reg != rcg->ns_reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) regmap_read(rcg->clkr.regmap, rcg->clkr.enable_reg, &mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) mode = ns;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) mode = reg_to_mnctr_mode(mn, mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) return calc_rate(parent_rate, m, n, mode, pre_div);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) static unsigned long
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) clk_dyn_rcg_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) struct clk_dyn_rcg *rcg = to_clk_dyn_rcg(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) u32 m, n, pre_div, ns, md, mode, reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) int bank;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) struct mn *mn;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) bool banked_p = !!rcg->p[1].pre_div_width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) bool banked_mn = !!rcg->mn[1].width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) regmap_read(rcg->clkr.regmap, rcg->bank_reg, ®);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) bank = reg_to_bank(rcg, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) regmap_read(rcg->clkr.regmap, rcg->ns_reg[bank], &ns);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) m = n = pre_div = mode = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) if (banked_mn) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) mn = &rcg->mn[bank];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) regmap_read(rcg->clkr.regmap, rcg->md_reg[bank], &md);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) m = md_to_m(mn, md);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) n = ns_m_to_n(mn, ns, m);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) /* Two NS registers means mode control is in NS register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) if (rcg->ns_reg[0] != rcg->ns_reg[1])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) reg = ns;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) mode = reg_to_mnctr_mode(mn, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) if (banked_p)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) pre_div = ns_to_pre_div(&rcg->p[bank], ns);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) return calc_rate(parent_rate, m, n, mode, pre_div);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) static int _freq_tbl_determine_rate(struct clk_hw *hw, const struct freq_tbl *f,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) struct clk_rate_request *req,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) const struct parent_map *parent_map)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) unsigned long clk_flags, rate = req->rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) struct clk_hw *p;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) int index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) f = qcom_find_freq(f, rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) if (!f)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) index = qcom_find_src_index(hw, parent_map, f->src);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) if (index < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) return index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) clk_flags = clk_hw_get_flags(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) p = clk_hw_get_parent_by_index(hw, index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) if (clk_flags & CLK_SET_RATE_PARENT) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) rate = rate * f->pre_div;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) if (f->n) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) u64 tmp = rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) tmp = tmp * f->n;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) do_div(tmp, f->m);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) rate = tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) rate = clk_hw_get_rate(p);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) req->best_parent_hw = p;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) req->best_parent_rate = rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) req->rate = f->freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) static int clk_rcg_determine_rate(struct clk_hw *hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) struct clk_rate_request *req)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) struct clk_rcg *rcg = to_clk_rcg(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) return _freq_tbl_determine_rate(hw, rcg->freq_tbl, req,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) rcg->s.parent_map);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) static int clk_dyn_rcg_determine_rate(struct clk_hw *hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) struct clk_rate_request *req)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) struct clk_dyn_rcg *rcg = to_clk_dyn_rcg(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) u32 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) int bank;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) struct src_sel *s;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) regmap_read(rcg->clkr.regmap, rcg->bank_reg, ®);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) bank = reg_to_bank(rcg, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) s = &rcg->s[bank];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) return _freq_tbl_determine_rate(hw, rcg->freq_tbl, req, s->parent_map);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) static int clk_rcg_bypass_determine_rate(struct clk_hw *hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) struct clk_rate_request *req)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) struct clk_rcg *rcg = to_clk_rcg(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) const struct freq_tbl *f = rcg->freq_tbl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) struct clk_hw *p;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) int index = qcom_find_src_index(hw, rcg->s.parent_map, f->src);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) req->best_parent_hw = p = clk_hw_get_parent_by_index(hw, index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) req->best_parent_rate = clk_hw_round_rate(p, req->rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) req->rate = req->best_parent_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) static int __clk_rcg_set_rate(struct clk_rcg *rcg, const struct freq_tbl *f)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) u32 ns, md, ctl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) struct mn *mn = &rcg->mn;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) u32 mask = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) unsigned int reset_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) if (rcg->mn.reset_in_cc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) reset_reg = rcg->clkr.enable_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) reset_reg = rcg->ns_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) if (rcg->mn.width) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) mask = BIT(mn->mnctr_reset_bit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) regmap_update_bits(rcg->clkr.regmap, reset_reg, mask, mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) regmap_read(rcg->clkr.regmap, rcg->md_reg, &md);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) md = mn_to_md(mn, f->m, f->n, md);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) regmap_write(rcg->clkr.regmap, rcg->md_reg, md);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) regmap_read(rcg->clkr.regmap, rcg->ns_reg, &ns);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) /* MN counter mode is in hw.enable_reg sometimes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) if (rcg->clkr.enable_reg != rcg->ns_reg) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) regmap_read(rcg->clkr.regmap, rcg->clkr.enable_reg, &ctl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) ctl = mn_to_reg(mn, f->m, f->n, ctl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) regmap_write(rcg->clkr.regmap, rcg->clkr.enable_reg, ctl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) ns = mn_to_reg(mn, f->m, f->n, ns);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) ns = mn_to_ns(mn, f->m, f->n, ns);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) regmap_read(rcg->clkr.regmap, rcg->ns_reg, &ns);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) ns = pre_div_to_ns(&rcg->p, f->pre_div - 1, ns);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) regmap_write(rcg->clkr.regmap, rcg->ns_reg, ns);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) regmap_update_bits(rcg->clkr.regmap, reset_reg, mask, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) static int clk_rcg_set_rate(struct clk_hw *hw, unsigned long rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) unsigned long parent_rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) struct clk_rcg *rcg = to_clk_rcg(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) const struct freq_tbl *f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) f = qcom_find_freq(rcg->freq_tbl, rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) if (!f)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) return __clk_rcg_set_rate(rcg, f);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) static int clk_rcg_bypass_set_rate(struct clk_hw *hw, unsigned long rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) unsigned long parent_rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) struct clk_rcg *rcg = to_clk_rcg(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) return __clk_rcg_set_rate(rcg, rcg->freq_tbl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) static int clk_rcg_bypass2_determine_rate(struct clk_hw *hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) struct clk_rate_request *req)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) struct clk_hw *p;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) p = req->best_parent_hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) req->best_parent_rate = clk_hw_round_rate(p, req->rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) req->rate = req->best_parent_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) static int clk_rcg_bypass2_set_rate(struct clk_hw *hw, unsigned long rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) unsigned long parent_rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) struct clk_rcg *rcg = to_clk_rcg(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) struct freq_tbl f = { 0 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) u32 ns, src;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) int i, ret, num_parents = clk_hw_get_num_parents(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) ret = regmap_read(rcg->clkr.regmap, rcg->ns_reg, &ns);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) src = ns_to_src(&rcg->s, ns);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) f.pre_div = ns_to_pre_div(&rcg->p, ns) + 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) for (i = 0; i < num_parents; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) if (src == rcg->s.parent_map[i].cfg) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) f.src = rcg->s.parent_map[i].src;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) return __clk_rcg_set_rate(rcg, &f);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) static int clk_rcg_bypass2_set_rate_and_parent(struct clk_hw *hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) unsigned long rate, unsigned long parent_rate, u8 index)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) /* Read the hardware to determine parent during set_rate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) return clk_rcg_bypass2_set_rate(hw, rate, parent_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) struct frac_entry {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) int num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) int den;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) static const struct frac_entry pixel_table[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) { 1, 2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) { 1, 3 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) { 3, 16 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) static int clk_rcg_pixel_determine_rate(struct clk_hw *hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) struct clk_rate_request *req)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) int delta = 100000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) const struct frac_entry *frac = pixel_table;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) unsigned long request, src_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) for (; frac->num; frac++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) request = (req->rate * frac->den) / frac->num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) src_rate = clk_hw_round_rate(req->best_parent_hw, request);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) if ((src_rate < (request - delta)) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) (src_rate > (request + delta)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) req->best_parent_rate = src_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) req->rate = (src_rate * frac->num) / frac->den;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) static int clk_rcg_pixel_set_rate(struct clk_hw *hw, unsigned long rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) unsigned long parent_rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) struct clk_rcg *rcg = to_clk_rcg(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) int delta = 100000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) const struct frac_entry *frac = pixel_table;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) unsigned long request;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) struct freq_tbl f = { 0 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) u32 ns, src;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) int i, ret, num_parents = clk_hw_get_num_parents(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) ret = regmap_read(rcg->clkr.regmap, rcg->ns_reg, &ns);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) src = ns_to_src(&rcg->s, ns);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) for (i = 0; i < num_parents; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) if (src == rcg->s.parent_map[i].cfg) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) f.src = rcg->s.parent_map[i].src;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) /* bypass the pre divider */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) f.pre_div = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) /* let us find appropriate m/n values for this */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) for (; frac->num; frac++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) request = (rate * frac->den) / frac->num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) if ((parent_rate < (request - delta)) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) (parent_rate > (request + delta)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) f.m = frac->num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) f.n = frac->den;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) return __clk_rcg_set_rate(rcg, &f);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) static int clk_rcg_pixel_set_rate_and_parent(struct clk_hw *hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) unsigned long rate, unsigned long parent_rate, u8 index)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) return clk_rcg_pixel_set_rate(hw, rate, parent_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) static int clk_rcg_esc_determine_rate(struct clk_hw *hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) struct clk_rate_request *req)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) struct clk_rcg *rcg = to_clk_rcg(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) int pre_div_max = BIT(rcg->p.pre_div_width);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) int div;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) unsigned long src_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) if (req->rate == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) src_rate = clk_hw_get_rate(req->best_parent_hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) div = src_rate / req->rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) if (div >= 1 && div <= pre_div_max) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) req->best_parent_rate = src_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) req->rate = src_rate / div;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) static int clk_rcg_esc_set_rate(struct clk_hw *hw, unsigned long rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) unsigned long parent_rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) struct clk_rcg *rcg = to_clk_rcg(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) struct freq_tbl f = { 0 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) int pre_div_max = BIT(rcg->p.pre_div_width);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) int div;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) u32 ns;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) int i, ret, num_parents = clk_hw_get_num_parents(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) if (rate == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) ret = regmap_read(rcg->clkr.regmap, rcg->ns_reg, &ns);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) ns = ns_to_src(&rcg->s, ns);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) for (i = 0; i < num_parents; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) if (ns == rcg->s.parent_map[i].cfg) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) f.src = rcg->s.parent_map[i].src;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) div = parent_rate / rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) if (div >= 1 && div <= pre_div_max) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) f.pre_div = div;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) return __clk_rcg_set_rate(rcg, &f);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) static int clk_rcg_esc_set_rate_and_parent(struct clk_hw *hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) unsigned long rate, unsigned long parent_rate, u8 index)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) return clk_rcg_esc_set_rate(hw, rate, parent_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) * This type of clock has a glitch-free mux that switches between the output of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) * the M/N counter and an always on clock source (XO). When clk_set_rate() is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) * called we need to make sure that we don't switch to the M/N counter if it
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) * isn't clocking because the mux will get stuck and the clock will stop
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) * outputting a clock. This can happen if the framework isn't aware that this
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) * clock is on and so clk_set_rate() doesn't turn on the new parent. To fix
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) * this we switch the mux in the enable/disable ops and reprogram the M/N
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) * counter in the set_rate op. We also make sure to switch away from the M/N
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) * counter in set_rate if software thinks the clock is off.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) static int clk_rcg_lcc_set_rate(struct clk_hw *hw, unsigned long rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) unsigned long parent_rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) struct clk_rcg *rcg = to_clk_rcg(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) const struct freq_tbl *f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) u32 gfm = BIT(10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) f = qcom_find_freq(rcg->freq_tbl, rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) if (!f)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) /* Switch to XO to avoid glitches */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) regmap_update_bits(rcg->clkr.regmap, rcg->ns_reg, gfm, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) ret = __clk_rcg_set_rate(rcg, f);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) /* Switch back to M/N if it's clocking */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) if (__clk_is_enabled(hw->clk))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) regmap_update_bits(rcg->clkr.regmap, rcg->ns_reg, gfm, gfm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) static int clk_rcg_lcc_enable(struct clk_hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) struct clk_rcg *rcg = to_clk_rcg(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) u32 gfm = BIT(10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) /* Use M/N */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) return regmap_update_bits(rcg->clkr.regmap, rcg->ns_reg, gfm, gfm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) static void clk_rcg_lcc_disable(struct clk_hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) struct clk_rcg *rcg = to_clk_rcg(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) u32 gfm = BIT(10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) /* Use XO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) regmap_update_bits(rcg->clkr.regmap, rcg->ns_reg, gfm, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) static int __clk_dyn_rcg_set_rate(struct clk_hw *hw, unsigned long rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) struct clk_dyn_rcg *rcg = to_clk_dyn_rcg(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) const struct freq_tbl *f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) f = qcom_find_freq(rcg->freq_tbl, rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) if (!f)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) return configure_bank(rcg, f);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) static int clk_dyn_rcg_set_rate(struct clk_hw *hw, unsigned long rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) unsigned long parent_rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) return __clk_dyn_rcg_set_rate(hw, rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) static int clk_dyn_rcg_set_rate_and_parent(struct clk_hw *hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) unsigned long rate, unsigned long parent_rate, u8 index)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) return __clk_dyn_rcg_set_rate(hw, rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) const struct clk_ops clk_rcg_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) .enable = clk_enable_regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) .disable = clk_disable_regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) .get_parent = clk_rcg_get_parent,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) .set_parent = clk_rcg_set_parent,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) .recalc_rate = clk_rcg_recalc_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) .determine_rate = clk_rcg_determine_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) .set_rate = clk_rcg_set_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) EXPORT_SYMBOL_GPL(clk_rcg_ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) const struct clk_ops clk_rcg_bypass_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) .enable = clk_enable_regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) .disable = clk_disable_regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) .get_parent = clk_rcg_get_parent,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) .set_parent = clk_rcg_set_parent,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) .recalc_rate = clk_rcg_recalc_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) .determine_rate = clk_rcg_bypass_determine_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) .set_rate = clk_rcg_bypass_set_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) EXPORT_SYMBOL_GPL(clk_rcg_bypass_ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) const struct clk_ops clk_rcg_bypass2_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) .enable = clk_enable_regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) .disable = clk_disable_regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) .get_parent = clk_rcg_get_parent,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) .set_parent = clk_rcg_set_parent,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) .recalc_rate = clk_rcg_recalc_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) .determine_rate = clk_rcg_bypass2_determine_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) .set_rate = clk_rcg_bypass2_set_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) .set_rate_and_parent = clk_rcg_bypass2_set_rate_and_parent,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) EXPORT_SYMBOL_GPL(clk_rcg_bypass2_ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) const struct clk_ops clk_rcg_pixel_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) .enable = clk_enable_regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) .disable = clk_disable_regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) .get_parent = clk_rcg_get_parent,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) .set_parent = clk_rcg_set_parent,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) .recalc_rate = clk_rcg_recalc_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) .determine_rate = clk_rcg_pixel_determine_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) .set_rate = clk_rcg_pixel_set_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) .set_rate_and_parent = clk_rcg_pixel_set_rate_and_parent,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) EXPORT_SYMBOL_GPL(clk_rcg_pixel_ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) const struct clk_ops clk_rcg_esc_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) .enable = clk_enable_regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) .disable = clk_disable_regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) .get_parent = clk_rcg_get_parent,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) .set_parent = clk_rcg_set_parent,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) .recalc_rate = clk_rcg_recalc_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) .determine_rate = clk_rcg_esc_determine_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) .set_rate = clk_rcg_esc_set_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) .set_rate_and_parent = clk_rcg_esc_set_rate_and_parent,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) EXPORT_SYMBOL_GPL(clk_rcg_esc_ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) const struct clk_ops clk_rcg_lcc_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) .enable = clk_rcg_lcc_enable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) .disable = clk_rcg_lcc_disable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) .get_parent = clk_rcg_get_parent,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) .set_parent = clk_rcg_set_parent,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) .recalc_rate = clk_rcg_recalc_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) .determine_rate = clk_rcg_determine_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) .set_rate = clk_rcg_lcc_set_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) EXPORT_SYMBOL_GPL(clk_rcg_lcc_ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) const struct clk_ops clk_dyn_rcg_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) .enable = clk_enable_regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) .is_enabled = clk_is_enabled_regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) .disable = clk_disable_regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) .get_parent = clk_dyn_rcg_get_parent,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) .set_parent = clk_dyn_rcg_set_parent,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) .recalc_rate = clk_dyn_rcg_recalc_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) .determine_rate = clk_dyn_rcg_determine_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) .set_rate = clk_dyn_rcg_set_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) .set_rate_and_parent = clk_dyn_rcg_set_rate_and_parent,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) EXPORT_SYMBOL_GPL(clk_dyn_rcg_ops);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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