Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) /* SPDX-License-Identifier: GPL-2.0-only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3)  * Copyright (c) 2013, The Linux Foundation. All rights reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6) #ifndef __QCOM_CLK_PLL_H__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7) #define __QCOM_CLK_PLL_H__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9) #include <linux/clk-provider.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include "clk-regmap.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)  * struct pll_freq_tbl - PLL frequency table
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)  * @l: L value
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)  * @m: M value
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)  * @n: N value
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)  * @ibits: internal values
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) struct pll_freq_tbl {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) 	unsigned long freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) 	u16 l;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) 	u16 m;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) 	u16 n;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) 	u32 ibits;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)  * struct clk_pll - phase locked loop (PLL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)  * @l_reg: L register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)  * @m_reg: M register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)  * @n_reg: N register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)  * @config_reg: config register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)  * @mode_reg: mode register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)  * @status_reg: status register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)  * @status_bit: ANDed with @status_reg to determine if PLL is enabled
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)  * @freq_tbl: PLL frequency table
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37)  * @hw: handle between common and hardware-specific interfaces
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) struct clk_pll {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) 	u32	l_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) 	u32	m_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) 	u32	n_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) 	u32	config_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) 	u32	mode_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) 	u32	status_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) 	u8	status_bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) 	u8	post_div_width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) 	u8	post_div_shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) 	const struct pll_freq_tbl *freq_tbl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) 	struct clk_regmap clkr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) extern const struct clk_ops clk_pll_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) extern const struct clk_ops clk_pll_vote_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) extern const struct clk_ops clk_pll_sr2_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define to_clk_pll(_hw) container_of(to_clk_regmap(_hw), struct clk_pll, clkr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) struct pll_config {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) 	u16 l;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) 	u32 m;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) 	u32 n;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) 	u32 vco_val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) 	u32 vco_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) 	u32 pre_div_val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) 	u32 pre_div_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) 	u32 post_div_val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) 	u32 post_div_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) 	u32 mn_ena_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) 	u32 main_output_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) 	u32 aux_output_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) void clk_pll_configure_sr(struct clk_pll *pll, struct regmap *regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) 		const struct pll_config *config, bool fsm_mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) void clk_pll_configure_sr_hpm_lp(struct clk_pll *pll, struct regmap *regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) 		const struct pll_config *config, bool fsm_mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #endif