^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (c) 2013, The Linux Foundation. All rights reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include <linux/bitops.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/bug.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/export.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/clk-provider.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/regmap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <asm/div64.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include "clk-pll.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include "common.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define PLL_OUTCTRL BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define PLL_BYPASSNL BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define PLL_RESET_N BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) static int clk_pll_enable(struct clk_hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) struct clk_pll *pll = to_clk_pll(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) u32 mask, val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) mask = PLL_OUTCTRL | PLL_RESET_N | PLL_BYPASSNL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) ret = regmap_read(pll->clkr.regmap, pll->mode_reg, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) /* Skip if already enabled or in FSM mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) if ((val & mask) == mask || val & PLL_VOTE_FSM_ENA)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) /* Disable PLL bypass mode. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) ret = regmap_update_bits(pll->clkr.regmap, pll->mode_reg, PLL_BYPASSNL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) PLL_BYPASSNL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) * H/W requires a 5us delay between disabling the bypass and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) * de-asserting the reset. Delay 10us just to be safe.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) udelay(10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) /* De-assert active-low PLL reset. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) ret = regmap_update_bits(pll->clkr.regmap, pll->mode_reg, PLL_RESET_N,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) PLL_RESET_N);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) /* Wait until PLL is locked. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) udelay(50);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) /* Enable PLL output. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) return regmap_update_bits(pll->clkr.regmap, pll->mode_reg, PLL_OUTCTRL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) PLL_OUTCTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) static void clk_pll_disable(struct clk_hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) struct clk_pll *pll = to_clk_pll(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) u32 mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) regmap_read(pll->clkr.regmap, pll->mode_reg, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) /* Skip if in FSM mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) if (val & PLL_VOTE_FSM_ENA)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) mask = PLL_OUTCTRL | PLL_RESET_N | PLL_BYPASSNL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) regmap_update_bits(pll->clkr.regmap, pll->mode_reg, mask, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) static unsigned long
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) clk_pll_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) struct clk_pll *pll = to_clk_pll(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) u32 l, m, n, config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) unsigned long rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) u64 tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) regmap_read(pll->clkr.regmap, pll->l_reg, &l);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) regmap_read(pll->clkr.regmap, pll->m_reg, &m);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) regmap_read(pll->clkr.regmap, pll->n_reg, &n);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) l &= 0x3ff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) m &= 0x7ffff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) n &= 0x7ffff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) rate = parent_rate * l;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) if (n) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) tmp = parent_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) tmp *= m;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) do_div(tmp, n);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) rate += tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) if (pll->post_div_width) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) regmap_read(pll->clkr.regmap, pll->config_reg, &config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) config >>= pll->post_div_shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) config &= BIT(pll->post_div_width) - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) rate /= config + 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) return rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) static const
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) struct pll_freq_tbl *find_freq(const struct pll_freq_tbl *f, unsigned long rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) if (!f)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) for (; f->freq; f++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) if (rate <= f->freq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) return f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) clk_pll_determine_rate(struct clk_hw *hw, struct clk_rate_request *req)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) struct clk_pll *pll = to_clk_pll(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) const struct pll_freq_tbl *f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) f = find_freq(pll->freq_tbl, req->rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) if (!f)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) req->rate = clk_pll_recalc_rate(hw, req->best_parent_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) req->rate = f->freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) clk_pll_set_rate(struct clk_hw *hw, unsigned long rate, unsigned long p_rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) struct clk_pll *pll = to_clk_pll(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) const struct pll_freq_tbl *f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) bool enabled;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) u32 mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) u32 enable_mask = PLL_OUTCTRL | PLL_BYPASSNL | PLL_RESET_N;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) f = find_freq(pll->freq_tbl, rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) if (!f)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) regmap_read(pll->clkr.regmap, pll->mode_reg, &mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) enabled = (mode & enable_mask) == enable_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) if (enabled)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) clk_pll_disable(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) regmap_update_bits(pll->clkr.regmap, pll->l_reg, 0x3ff, f->l);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) regmap_update_bits(pll->clkr.regmap, pll->m_reg, 0x7ffff, f->m);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) regmap_update_bits(pll->clkr.regmap, pll->n_reg, 0x7ffff, f->n);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) regmap_write(pll->clkr.regmap, pll->config_reg, f->ibits);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) if (enabled)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) clk_pll_enable(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) const struct clk_ops clk_pll_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) .enable = clk_pll_enable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) .disable = clk_pll_disable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) .recalc_rate = clk_pll_recalc_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) .determine_rate = clk_pll_determine_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) .set_rate = clk_pll_set_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) EXPORT_SYMBOL_GPL(clk_pll_ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) static int wait_for_pll(struct clk_pll *pll)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) int count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) const char *name = clk_hw_get_name(&pll->clkr.hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) /* Wait for pll to enable. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) for (count = 200; count > 0; count--) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) ret = regmap_read(pll->clkr.regmap, pll->status_reg, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) if (val & BIT(pll->status_bit))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) udelay(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) WARN(1, "%s didn't enable after voting for it!\n", name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) return -ETIMEDOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) static int clk_pll_vote_enable(struct clk_hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) struct clk_pll *p = to_clk_pll(clk_hw_get_parent(hw));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) ret = clk_enable_regmap(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) return wait_for_pll(p);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) const struct clk_ops clk_pll_vote_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) .enable = clk_pll_vote_enable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) .disable = clk_disable_regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) EXPORT_SYMBOL_GPL(clk_pll_vote_ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) static void clk_pll_configure(struct clk_pll *pll, struct regmap *regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) const struct pll_config *config)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) u32 mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) regmap_write(regmap, pll->l_reg, config->l);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) regmap_write(regmap, pll->m_reg, config->m);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) regmap_write(regmap, pll->n_reg, config->n);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) val = config->vco_val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) val |= config->pre_div_val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) val |= config->post_div_val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) val |= config->mn_ena_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) val |= config->main_output_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) val |= config->aux_output_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) mask = config->vco_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) mask |= config->pre_div_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) mask |= config->post_div_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) mask |= config->mn_ena_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) mask |= config->main_output_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) mask |= config->aux_output_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) regmap_update_bits(regmap, pll->config_reg, mask, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) void clk_pll_configure_sr(struct clk_pll *pll, struct regmap *regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) const struct pll_config *config, bool fsm_mode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) clk_pll_configure(pll, regmap, config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) if (fsm_mode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) qcom_pll_set_fsm_mode(regmap, pll->mode_reg, 1, 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) EXPORT_SYMBOL_GPL(clk_pll_configure_sr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) void clk_pll_configure_sr_hpm_lp(struct clk_pll *pll, struct regmap *regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) const struct pll_config *config, bool fsm_mode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) clk_pll_configure(pll, regmap, config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) if (fsm_mode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) qcom_pll_set_fsm_mode(regmap, pll->mode_reg, 1, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) EXPORT_SYMBOL_GPL(clk_pll_configure_sr_hpm_lp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) static int clk_pll_sr2_enable(struct clk_hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) struct clk_pll *pll = to_clk_pll(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) u32 mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) ret = regmap_read(pll->clkr.regmap, pll->mode_reg, &mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) /* Disable PLL bypass mode. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) ret = regmap_update_bits(pll->clkr.regmap, pll->mode_reg, PLL_BYPASSNL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) PLL_BYPASSNL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) * H/W requires a 5us delay between disabling the bypass and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) * de-asserting the reset. Delay 10us just to be safe.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) udelay(10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) /* De-assert active-low PLL reset. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) ret = regmap_update_bits(pll->clkr.regmap, pll->mode_reg, PLL_RESET_N,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) PLL_RESET_N);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) ret = wait_for_pll(pll);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) /* Enable PLL output. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) return regmap_update_bits(pll->clkr.regmap, pll->mode_reg, PLL_OUTCTRL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) PLL_OUTCTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) clk_pll_sr2_set_rate(struct clk_hw *hw, unsigned long rate, unsigned long prate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) struct clk_pll *pll = to_clk_pll(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) const struct pll_freq_tbl *f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) bool enabled;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) u32 mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) u32 enable_mask = PLL_OUTCTRL | PLL_BYPASSNL | PLL_RESET_N;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) f = find_freq(pll->freq_tbl, rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) if (!f)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) regmap_read(pll->clkr.regmap, pll->mode_reg, &mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) enabled = (mode & enable_mask) == enable_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) if (enabled)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) clk_pll_disable(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) regmap_update_bits(pll->clkr.regmap, pll->l_reg, 0x3ff, f->l);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) regmap_update_bits(pll->clkr.regmap, pll->m_reg, 0x7ffff, f->m);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) regmap_update_bits(pll->clkr.regmap, pll->n_reg, 0x7ffff, f->n);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) if (enabled)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) clk_pll_sr2_enable(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) const struct clk_ops clk_pll_sr2_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) .enable = clk_pll_sr2_enable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) .disable = clk_pll_disable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) .set_rate = clk_pll_sr2_set_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) .recalc_rate = clk_pll_recalc_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) .determine_rate = clk_pll_determine_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) EXPORT_SYMBOL_GPL(clk_pll_sr2_ops);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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