^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) // Copyright (c) 2018, The Linux Foundation. All rights reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/clk-provider.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/spinlock.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <asm/krait-l2-accessors.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include "clk-krait.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) /* Secondary and primary muxes share the same cp15 register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) static DEFINE_SPINLOCK(krait_clock_reg_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define LPL_SHIFT 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) static void __krait_mux_set_sel(struct krait_mux_clk *mux, int sel)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) u32 regval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) spin_lock_irqsave(&krait_clock_reg_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) regval = krait_get_l2_indirect_reg(mux->offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) regval &= ~(mux->mask << mux->shift);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) regval |= (sel & mux->mask) << mux->shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) if (mux->lpl) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) regval &= ~(mux->mask << (mux->shift + LPL_SHIFT));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) regval |= (sel & mux->mask) << (mux->shift + LPL_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) krait_set_l2_indirect_reg(mux->offset, regval);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) spin_unlock_irqrestore(&krait_clock_reg_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) /* Wait for switch to complete. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) mb();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) udelay(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) static int krait_mux_set_parent(struct clk_hw *hw, u8 index)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) struct krait_mux_clk *mux = to_krait_mux_clk(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) u32 sel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) sel = clk_mux_index_to_val(mux->parent_map, 0, index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) mux->en_mask = sel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) /* Don't touch mux if CPU is off as it won't work */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) if (__clk_is_enabled(hw->clk))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) __krait_mux_set_sel(mux, sel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) mux->reparent = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) static u8 krait_mux_get_parent(struct clk_hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) struct krait_mux_clk *mux = to_krait_mux_clk(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) u32 sel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) sel = krait_get_l2_indirect_reg(mux->offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) sel >>= mux->shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) sel &= mux->mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) mux->en_mask = sel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) return clk_mux_val_to_index(hw, mux->parent_map, 0, sel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) const struct clk_ops krait_mux_clk_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) .set_parent = krait_mux_set_parent,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) .get_parent = krait_mux_get_parent,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) .determine_rate = __clk_mux_determine_rate_closest,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) EXPORT_SYMBOL_GPL(krait_mux_clk_ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) /* The divider can divide by 2, 4, 6 and 8. But we only really need div-2. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) static long krait_div2_round_rate(struct clk_hw *hw, unsigned long rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) unsigned long *parent_rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) *parent_rate = clk_hw_round_rate(clk_hw_get_parent(hw), rate * 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) return DIV_ROUND_UP(*parent_rate, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) static int krait_div2_set_rate(struct clk_hw *hw, unsigned long rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) unsigned long parent_rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) struct krait_div2_clk *d = to_krait_div2_clk(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) u32 mask = BIT(d->width) - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) if (d->lpl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) mask = mask << (d->shift + LPL_SHIFT) | mask << d->shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) spin_lock_irqsave(&krait_clock_reg_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) val = krait_get_l2_indirect_reg(d->offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) val &= ~mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) krait_set_l2_indirect_reg(d->offset, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) spin_unlock_irqrestore(&krait_clock_reg_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) static unsigned long
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) krait_div2_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) struct krait_div2_clk *d = to_krait_div2_clk(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) u32 mask = BIT(d->width) - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) u32 div;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) div = krait_get_l2_indirect_reg(d->offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) div >>= d->shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) div &= mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) div = (div + 1) * 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) return DIV_ROUND_UP(parent_rate, div);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) const struct clk_ops krait_div2_clk_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) .round_rate = krait_div2_round_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) .set_rate = krait_div2_set_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) .recalc_rate = krait_div2_recalc_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) EXPORT_SYMBOL_GPL(krait_div2_clk_ops);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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