^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (c) 2020, The Linux Foundation. All rights reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Each of the CPU clusters (Power and Perf) on msm8996 are
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * clocked via 2 PLLs, a primary and alternate. There are also
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * 2 Mux'es, a primary and secondary all connected together
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * as shown below
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * +-------+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) * XO | |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) * +------------------>0 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) * | |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) * PLL/2 | SMUX +----+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) * +------->1 | |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) * | | | |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) * | +-------+ | +-------+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) * | +---->0 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) * | | |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) * +---------------+ | +----------->1 | CPU clk
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) * |Primary PLL +----+ PLL_EARLY | | +------>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) * | +------+-----------+ +------>2 PMUX |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) * +---------------+ | | | |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) * | +------+ | +-->3 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) * +--^+ ACD +-----+ | +-------+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) * +---------------+ +------+ |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) * |Alt PLL | |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) * | +---------------------------+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) * +---------------+ PLL_EARLY
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) * The primary PLL is what drives the CPU clk, except for times
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) * when we are reprogramming the PLL itself (for rate changes) when
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) * we temporarily switch to an alternate PLL.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) * The primary PLL operates on a single VCO range, between 600MHz
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) * and 3GHz. However the CPUs do support OPPs with frequencies
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) * between 300MHz and 600MHz. In order to support running the CPUs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) * at those frequencies we end up having to lock the PLL at twice
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) * the rate and drive the CPU clk via the PLL/2 output and SMUX.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) * So for frequencies above 600MHz we follow the following path
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) * Primary PLL --> PLL_EARLY --> PMUX(1) --> CPU clk
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) * and for frequencies between 300MHz and 600MHz we follow
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) * Primary PLL --> PLL/2 --> SMUX(1) --> PMUX(0) --> CPU clk
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) * ACD stands for Adaptive Clock Distribution and is used to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) * detect voltage droops.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #include <linux/clk-provider.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #include <linux/regmap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #include <soc/qcom/kryo-l2-accessors.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #include "clk-alpha-pll.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #include "clk-regmap.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) enum _pmux_input {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) DIV_2_INDEX = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) PLL_INDEX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) ACD_INDEX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) ALT_INDEX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) NUM_OF_PMUX_INPUTS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define DIV_2_THRESHOLD 600000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define PWRCL_REG_OFFSET 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define PERFCL_REG_OFFSET 0x80000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define MUX_OFFSET 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define ALT_PLL_OFFSET 0x100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define SSSCTL_OFFSET 0x160
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) static const u8 prim_pll_regs[PLL_OFF_MAX_REGS] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) [PLL_OFF_L_VAL] = 0x04,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) [PLL_OFF_ALPHA_VAL] = 0x08,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) [PLL_OFF_USER_CTL] = 0x10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) [PLL_OFF_CONFIG_CTL] = 0x18,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) [PLL_OFF_CONFIG_CTL_U] = 0x1c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) [PLL_OFF_TEST_CTL] = 0x20,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) [PLL_OFF_TEST_CTL_U] = 0x24,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) [PLL_OFF_STATUS] = 0x28,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) static const u8 alt_pll_regs[PLL_OFF_MAX_REGS] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) [PLL_OFF_L_VAL] = 0x04,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) [PLL_OFF_ALPHA_VAL] = 0x08,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) [PLL_OFF_ALPHA_VAL_U] = 0x0c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) [PLL_OFF_USER_CTL] = 0x10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) [PLL_OFF_USER_CTL_U] = 0x14,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) [PLL_OFF_CONFIG_CTL] = 0x18,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) [PLL_OFF_TEST_CTL] = 0x20,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) [PLL_OFF_TEST_CTL_U] = 0x24,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) [PLL_OFF_STATUS] = 0x28,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) /* PLLs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) static const struct alpha_pll_config hfpll_config = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) .l = 60,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) .config_ctl_val = 0x200d4aa8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) .config_ctl_hi_val = 0x006,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) .pre_div_mask = BIT(12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) .post_div_mask = 0x3 << 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) .post_div_val = 0x1 << 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) .main_output_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) .early_output_mask = BIT(3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) static struct clk_alpha_pll perfcl_pll = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) .offset = PERFCL_REG_OFFSET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) .regs = prim_pll_regs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) .flags = SUPPORTS_DYNAMIC_UPDATE | SUPPORTS_FSM_MODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) .name = "perfcl_pll",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) .parent_names = (const char *[]){ "xo" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) .ops = &clk_alpha_pll_huayra_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) static struct clk_alpha_pll pwrcl_pll = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) .offset = PWRCL_REG_OFFSET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) .regs = prim_pll_regs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) .flags = SUPPORTS_DYNAMIC_UPDATE | SUPPORTS_FSM_MODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) .name = "pwrcl_pll",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) .parent_names = (const char *[]){ "xo" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) .ops = &clk_alpha_pll_huayra_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) static const struct pll_vco alt_pll_vco_modes[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) VCO(3, 250000000, 500000000),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) VCO(2, 500000000, 750000000),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) VCO(1, 750000000, 1000000000),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) VCO(0, 1000000000, 2150400000),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) static const struct alpha_pll_config altpll_config = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) .l = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) .vco_val = 0x3 << 20,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) .vco_mask = 0x3 << 20,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) .config_ctl_val = 0x4001051b,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) .post_div_mask = 0x3 << 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) .post_div_val = 0x1 << 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) .main_output_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) .early_output_mask = BIT(3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) static struct clk_alpha_pll perfcl_alt_pll = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) .offset = PERFCL_REG_OFFSET + ALT_PLL_OFFSET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) .regs = alt_pll_regs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) .vco_table = alt_pll_vco_modes,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) .num_vco = ARRAY_SIZE(alt_pll_vco_modes),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) .flags = SUPPORTS_OFFLINE_REQ | SUPPORTS_FSM_MODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) .clkr.hw.init = &(struct clk_init_data) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) .name = "perfcl_alt_pll",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) .parent_names = (const char *[]){ "xo" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) .ops = &clk_alpha_pll_hwfsm_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) static struct clk_alpha_pll pwrcl_alt_pll = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) .offset = PWRCL_REG_OFFSET + ALT_PLL_OFFSET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) .regs = alt_pll_regs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) .vco_table = alt_pll_vco_modes,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) .num_vco = ARRAY_SIZE(alt_pll_vco_modes),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) .flags = SUPPORTS_OFFLINE_REQ | SUPPORTS_FSM_MODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) .clkr.hw.init = &(struct clk_init_data) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) .name = "pwrcl_alt_pll",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) .parent_names = (const char *[]){ "xo" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) .ops = &clk_alpha_pll_hwfsm_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) struct clk_cpu_8996_mux {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) u32 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) u8 shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) u8 width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) struct notifier_block nb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) struct clk_hw *pll;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) struct clk_hw *pll_div_2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) struct clk_regmap clkr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) static int cpu_clk_notifier_cb(struct notifier_block *nb, unsigned long event,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) void *data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) #define to_clk_cpu_8996_mux_nb(_nb) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) container_of(_nb, struct clk_cpu_8996_mux, nb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) static inline struct clk_cpu_8996_mux *to_clk_cpu_8996_mux_hw(struct clk_hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) return container_of(to_clk_regmap(hw), struct clk_cpu_8996_mux, clkr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) static u8 clk_cpu_8996_mux_get_parent(struct clk_hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) struct clk_regmap *clkr = to_clk_regmap(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) struct clk_cpu_8996_mux *cpuclk = to_clk_cpu_8996_mux_hw(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) u32 mask = GENMASK(cpuclk->width - 1, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) regmap_read(clkr->regmap, cpuclk->reg, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) val >>= cpuclk->shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) return val & mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) static int clk_cpu_8996_mux_set_parent(struct clk_hw *hw, u8 index)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) struct clk_regmap *clkr = to_clk_regmap(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) struct clk_cpu_8996_mux *cpuclk = to_clk_cpu_8996_mux_hw(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) u32 mask = GENMASK(cpuclk->width + cpuclk->shift - 1, cpuclk->shift);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) val = index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) val <<= cpuclk->shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) return regmap_update_bits(clkr->regmap, cpuclk->reg, mask, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) static int clk_cpu_8996_mux_determine_rate(struct clk_hw *hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) struct clk_rate_request *req)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) struct clk_cpu_8996_mux *cpuclk = to_clk_cpu_8996_mux_hw(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) struct clk_hw *parent = cpuclk->pll;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) if (cpuclk->pll_div_2 && req->rate < DIV_2_THRESHOLD) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) if (req->rate < (DIV_2_THRESHOLD / 2))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) parent = cpuclk->pll_div_2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) req->best_parent_rate = clk_hw_round_rate(parent, req->rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) req->best_parent_hw = parent;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) static const struct clk_ops clk_cpu_8996_mux_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) .set_parent = clk_cpu_8996_mux_set_parent,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) .get_parent = clk_cpu_8996_mux_get_parent,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) .determine_rate = clk_cpu_8996_mux_determine_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) static struct clk_cpu_8996_mux pwrcl_smux = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) .reg = PWRCL_REG_OFFSET + MUX_OFFSET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) .shift = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) .width = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) .clkr.hw.init = &(struct clk_init_data) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) .name = "pwrcl_smux",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) "xo",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) "pwrcl_pll_main",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) .num_parents = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) .ops = &clk_cpu_8996_mux_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) static struct clk_cpu_8996_mux perfcl_smux = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) .reg = PERFCL_REG_OFFSET + MUX_OFFSET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) .shift = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) .width = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) .clkr.hw.init = &(struct clk_init_data) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) .name = "perfcl_smux",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) "xo",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) "perfcl_pll_main",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) .num_parents = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) .ops = &clk_cpu_8996_mux_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) static struct clk_cpu_8996_mux pwrcl_pmux = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) .reg = PWRCL_REG_OFFSET + MUX_OFFSET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) .shift = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) .width = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) .pll = &pwrcl_pll.clkr.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) .pll_div_2 = &pwrcl_smux.clkr.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) .nb.notifier_call = cpu_clk_notifier_cb,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) .clkr.hw.init = &(struct clk_init_data) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) .name = "pwrcl_pmux",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) "pwrcl_smux",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) "pwrcl_pll",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) "pwrcl_pll_acd",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) "pwrcl_alt_pll",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) .num_parents = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) .ops = &clk_cpu_8996_mux_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) /* CPU clock is critical and should never be gated */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) .flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) static struct clk_cpu_8996_mux perfcl_pmux = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) .reg = PERFCL_REG_OFFSET + MUX_OFFSET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) .shift = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) .width = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) .pll = &perfcl_pll.clkr.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) .pll_div_2 = &perfcl_smux.clkr.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) .nb.notifier_call = cpu_clk_notifier_cb,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) .clkr.hw.init = &(struct clk_init_data) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) .name = "perfcl_pmux",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) "perfcl_smux",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) "perfcl_pll",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) "perfcl_pll_acd",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) "perfcl_alt_pll",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) .num_parents = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) .ops = &clk_cpu_8996_mux_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) /* CPU clock is critical and should never be gated */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) .flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) static const struct regmap_config cpu_msm8996_regmap_config = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) .reg_bits = 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) .reg_stride = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) .val_bits = 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) .max_register = 0x80210,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) .fast_io = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) .val_format_endian = REGMAP_ENDIAN_LITTLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) static struct clk_regmap *cpu_msm8996_clks[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) &perfcl_pll.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) &pwrcl_pll.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) &perfcl_alt_pll.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) &pwrcl_alt_pll.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) &perfcl_smux.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) &pwrcl_smux.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) &perfcl_pmux.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) &pwrcl_pmux.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) static int qcom_cpu_clk_msm8996_register_clks(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) struct regmap *regmap)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) int i, ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) perfcl_smux.pll = clk_hw_register_fixed_factor(dev, "perfcl_pll_main",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) "perfcl_pll",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) 1, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) if (IS_ERR(perfcl_smux.pll)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) dev_err(dev, "Failed to initialize perfcl_pll_main\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) return PTR_ERR(perfcl_smux.pll);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) pwrcl_smux.pll = clk_hw_register_fixed_factor(dev, "pwrcl_pll_main",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) "pwrcl_pll",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) 1, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) if (IS_ERR(pwrcl_smux.pll)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) dev_err(dev, "Failed to initialize pwrcl_pll_main\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) clk_hw_unregister(perfcl_smux.pll);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) return PTR_ERR(pwrcl_smux.pll);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) for (i = 0; i < ARRAY_SIZE(cpu_msm8996_clks); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) ret = devm_clk_register_regmap(dev, cpu_msm8996_clks[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) clk_hw_unregister(perfcl_smux.pll);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) clk_hw_unregister(pwrcl_smux.pll);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) clk_alpha_pll_configure(&perfcl_pll, regmap, &hfpll_config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) clk_alpha_pll_configure(&pwrcl_pll, regmap, &hfpll_config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) clk_alpha_pll_configure(&perfcl_alt_pll, regmap, &altpll_config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) clk_alpha_pll_configure(&pwrcl_alt_pll, regmap, &altpll_config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) /* Enable alt PLLs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) clk_prepare_enable(pwrcl_alt_pll.clkr.hw.clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) clk_prepare_enable(perfcl_alt_pll.clkr.hw.clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) clk_notifier_register(pwrcl_pmux.clkr.hw.clk, &pwrcl_pmux.nb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) clk_notifier_register(perfcl_pmux.clkr.hw.clk, &perfcl_pmux.nb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) static int qcom_cpu_clk_msm8996_unregister_clks(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) ret = clk_notifier_unregister(pwrcl_pmux.clkr.hw.clk, &pwrcl_pmux.nb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) ret = clk_notifier_unregister(perfcl_pmux.clkr.hw.clk, &perfcl_pmux.nb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) clk_hw_unregister(perfcl_smux.pll);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) clk_hw_unregister(pwrcl_smux.pll);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) #define CPU_AFINITY_MASK 0xFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) #define PWRCL_CPU_REG_MASK 0x3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) #define PERFCL_CPU_REG_MASK 0x103
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) #define L2ACDCR_REG 0x580ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) #define L2ACDTD_REG 0x581ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) #define L2ACDDVMRC_REG 0x584ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) #define L2ACDSSCR_REG 0x589ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) static DEFINE_SPINLOCK(qcom_clk_acd_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) static void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) static void qcom_cpu_clk_msm8996_acd_init(void __iomem *base)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) u64 hwid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) spin_lock_irqsave(&qcom_clk_acd_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) hwid = read_cpuid_mpidr() & CPU_AFINITY_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) kryo_l2_set_indirect_reg(L2ACDTD_REG, 0x00006a11);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) kryo_l2_set_indirect_reg(L2ACDDVMRC_REG, 0x000e0f0f);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) kryo_l2_set_indirect_reg(L2ACDSSCR_REG, 0x00000601);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) if (PWRCL_CPU_REG_MASK == (hwid | PWRCL_CPU_REG_MASK)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) writel(0xf, base + PWRCL_REG_OFFSET + SSSCTL_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) kryo_l2_set_indirect_reg(L2ACDCR_REG, 0x002c5ffd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) if (PERFCL_CPU_REG_MASK == (hwid | PERFCL_CPU_REG_MASK)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) kryo_l2_set_indirect_reg(L2ACDCR_REG, 0x002c5ffd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) writel(0xf, base + PERFCL_REG_OFFSET + SSSCTL_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) spin_unlock_irqrestore(&qcom_clk_acd_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) static int cpu_clk_notifier_cb(struct notifier_block *nb, unsigned long event,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) void *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) struct clk_cpu_8996_mux *cpuclk = to_clk_cpu_8996_mux_nb(nb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) struct clk_notifier_data *cnd = data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) switch (event) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) case PRE_RATE_CHANGE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) ret = clk_cpu_8996_mux_set_parent(&cpuclk->clkr.hw, ALT_INDEX);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) qcom_cpu_clk_msm8996_acd_init(base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) case POST_RATE_CHANGE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) if (cnd->new_rate < DIV_2_THRESHOLD)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) ret = clk_cpu_8996_mux_set_parent(&cpuclk->clkr.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) DIV_2_INDEX);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) ret = clk_cpu_8996_mux_set_parent(&cpuclk->clkr.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) ACD_INDEX);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) return notifier_from_errno(ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) static int qcom_cpu_clk_msm8996_driver_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) struct regmap *regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) struct clk_hw_onecell_data *data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) struct device *dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) data = devm_kzalloc(dev, struct_size(data, hws, 2), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) if (!data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) base = devm_platform_ioremap_resource(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) if (IS_ERR(base))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) return PTR_ERR(base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) regmap = devm_regmap_init_mmio(dev, base, &cpu_msm8996_regmap_config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) if (IS_ERR(regmap))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) return PTR_ERR(regmap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) ret = qcom_cpu_clk_msm8996_register_clks(dev, regmap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) qcom_cpu_clk_msm8996_acd_init(base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) data->hws[0] = &pwrcl_pmux.clkr.hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) data->hws[1] = &perfcl_pmux.clkr.hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) data->num = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) return devm_of_clk_add_hw_provider(dev, of_clk_hw_onecell_get, data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) static int qcom_cpu_clk_msm8996_driver_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) return qcom_cpu_clk_msm8996_unregister_clks();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) static const struct of_device_id qcom_cpu_clk_msm8996_match_table[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) { .compatible = "qcom,msm8996-apcc" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) {}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) MODULE_DEVICE_TABLE(of, qcom_cpu_clk_msm8996_match_table);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) static struct platform_driver qcom_cpu_clk_msm8996_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) .probe = qcom_cpu_clk_msm8996_driver_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) .remove = qcom_cpu_clk_msm8996_driver_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) .name = "qcom-msm8996-apcc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) .of_match_table = qcom_cpu_clk_msm8996_match_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) module_platform_driver(qcom_cpu_clk_msm8996_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) MODULE_DESCRIPTION("QCOM MSM8996 CPU Clock Driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) MODULE_LICENSE("GPL v2");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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