Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) /* SPDX-License-Identifier: GPL-2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) /* Copyright (c) 2013, The Linux Foundation. All rights reserved. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4) #ifndef __QCOM_CLK_BRANCH_H__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5) #define __QCOM_CLK_BRANCH_H__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7) #include <linux/clk-provider.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9) #include "clk-regmap.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)  * struct clk_branch - gating clock with status bit and dynamic hardware gating
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)  * @hwcg_reg: dynamic hardware clock gating register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)  * @hwcg_bit: ORed with @hwcg_reg to enable dynamic hardware clock gating
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)  * @halt_reg: halt register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)  * @halt_bit: ANDed with @halt_reg to test for clock halted
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)  * @halt_check: type of halt checking to perform
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)  * @clkr: handle between common and hardware-specific interfaces
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)  * Clock which can gate its output.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) struct clk_branch {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) 	u32	hwcg_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) 	u32	halt_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) 	u8	hwcg_bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) 	u8	halt_bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) 	u8	halt_check;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define BRANCH_VOTED			BIT(7) /* Delay on disable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define BRANCH_HALT			0 /* pol: 1 = halt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define BRANCH_HALT_VOTED		(BRANCH_HALT | BRANCH_VOTED)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define BRANCH_HALT_ENABLE		1 /* pol: 0 = halt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define BRANCH_HALT_ENABLE_VOTED	(BRANCH_HALT_ENABLE | BRANCH_VOTED)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define BRANCH_HALT_DELAY		2 /* No bit to check; just delay */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define BRANCH_HALT_SKIP		3 /* Don't check halt bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) 	struct clk_regmap clkr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) extern const struct clk_ops clk_branch_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) extern const struct clk_ops clk_branch2_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) extern const struct clk_ops clk_branch_simple_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) extern const struct clk_ops clk_branch2_aon_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define to_clk_branch(_hw) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) 	container_of(to_clk_regmap(_hw), struct clk_branch, clkr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #endif