^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (c) 2013, The Linux Foundation. All rights reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include <linux/bitops.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/export.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/clk-provider.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/regmap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include "clk-branch.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) static bool clk_branch_in_hwcg_mode(const struct clk_branch *br)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) if (!br->hwcg_reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) regmap_read(br->clkr.regmap, br->hwcg_reg, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) return !!(val & BIT(br->hwcg_bit));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) static bool clk_branch_check_halt(const struct clk_branch *br, bool enabling)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) bool invert = (br->halt_check == BRANCH_HALT_ENABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) regmap_read(br->clkr.regmap, br->halt_reg, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) val &= BIT(br->halt_bit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) if (invert)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) val = !val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) return !!val == !enabling;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define BRANCH_CLK_OFF BIT(31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define BRANCH_NOC_FSM_STATUS_SHIFT 28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define BRANCH_NOC_FSM_STATUS_MASK 0x7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define BRANCH_NOC_FSM_STATUS_ON (0x2 << BRANCH_NOC_FSM_STATUS_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) static bool clk_branch2_check_halt(const struct clk_branch *br, bool enabling)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) u32 mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) mask = BRANCH_NOC_FSM_STATUS_MASK << BRANCH_NOC_FSM_STATUS_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) mask |= BRANCH_CLK_OFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) regmap_read(br->clkr.regmap, br->halt_reg, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) if (enabling) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) val &= mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) return (val & BRANCH_CLK_OFF) == 0 ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) val == BRANCH_NOC_FSM_STATUS_ON;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) return val & BRANCH_CLK_OFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) static int clk_branch_wait(const struct clk_branch *br, bool enabling,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) bool (check_halt)(const struct clk_branch *, bool))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) bool voted = br->halt_check & BRANCH_VOTED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) const char *name = clk_hw_get_name(&br->clkr.hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) * Skip checking halt bit if we're explicitly ignoring the bit or the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) * clock is in hardware gated mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) if (br->halt_check == BRANCH_HALT_SKIP || clk_branch_in_hwcg_mode(br))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) if (br->halt_check == BRANCH_HALT_DELAY || (!enabling && voted)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) udelay(10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) } else if (br->halt_check == BRANCH_HALT_ENABLE ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) br->halt_check == BRANCH_HALT ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) (enabling && voted)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) int count = 200;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) while (count-- > 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) if (check_halt(br, enabling))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) udelay(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) WARN(1, "%s status stuck at 'o%s'", name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) enabling ? "ff" : "n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) return -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) static int clk_branch_toggle(struct clk_hw *hw, bool en,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) bool (check_halt)(const struct clk_branch *, bool))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) struct clk_branch *br = to_clk_branch(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) if (en) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) ret = clk_enable_regmap(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) clk_disable_regmap(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) return clk_branch_wait(br, en, check_halt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) static int clk_branch_enable(struct clk_hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) return clk_branch_toggle(hw, true, clk_branch_check_halt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) static void clk_branch_disable(struct clk_hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) clk_branch_toggle(hw, false, clk_branch_check_halt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) const struct clk_ops clk_branch_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) .enable = clk_branch_enable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) .disable = clk_branch_disable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) .is_enabled = clk_is_enabled_regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) EXPORT_SYMBOL_GPL(clk_branch_ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) static int clk_branch2_enable(struct clk_hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) return clk_branch_toggle(hw, true, clk_branch2_check_halt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) static void clk_branch2_disable(struct clk_hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) clk_branch_toggle(hw, false, clk_branch2_check_halt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) const struct clk_ops clk_branch2_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) .enable = clk_branch2_enable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) .disable = clk_branch2_disable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) .is_enabled = clk_is_enabled_regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) EXPORT_SYMBOL_GPL(clk_branch2_ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) const struct clk_ops clk_branch2_aon_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) .enable = clk_branch2_enable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) .is_enabled = clk_is_enabled_regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) EXPORT_SYMBOL_GPL(clk_branch2_aon_ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) const struct clk_ops clk_branch_simple_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) .enable = clk_enable_regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) .disable = clk_disable_regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) .is_enabled = clk_is_enabled_regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) EXPORT_SYMBOL_GPL(clk_branch_simple_ops);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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