^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /* Copyright (c) 2015, 2018, The Linux Foundation. All rights reserved. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) #ifndef __QCOM_CLK_ALPHA_PLL_H__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) #define __QCOM_CLK_ALPHA_PLL_H__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include <linux/clk-provider.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include "clk-regmap.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) /* Alpha PLL types */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) CLK_ALPHA_PLL_TYPE_DEFAULT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) CLK_ALPHA_PLL_TYPE_HUAYRA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) CLK_ALPHA_PLL_TYPE_BRAMMO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) CLK_ALPHA_PLL_TYPE_FABIA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) CLK_ALPHA_PLL_TYPE_TRION,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) CLK_ALPHA_PLL_TYPE_LUCID = CLK_ALPHA_PLL_TYPE_TRION,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) CLK_ALPHA_PLL_TYPE_MAX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) PLL_OFF_L_VAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) PLL_OFF_CAL_L_VAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) PLL_OFF_ALPHA_VAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) PLL_OFF_ALPHA_VAL_U,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) PLL_OFF_USER_CTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) PLL_OFF_USER_CTL_U,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) PLL_OFF_USER_CTL_U1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) PLL_OFF_CONFIG_CTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) PLL_OFF_CONFIG_CTL_U,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) PLL_OFF_CONFIG_CTL_U1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) PLL_OFF_TEST_CTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) PLL_OFF_TEST_CTL_U,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) PLL_OFF_TEST_CTL_U1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) PLL_OFF_STATUS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) PLL_OFF_OPMODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) PLL_OFF_FRAC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) PLL_OFF_CAL_VAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) PLL_OFF_MAX_REGS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) extern const u8 clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_MAX][PLL_OFF_MAX_REGS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) struct pll_vco {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) unsigned long min_freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) unsigned long max_freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define VCO(a, b, c) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) .val = a,\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) .min_freq = b,\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) .max_freq = c,\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) * struct clk_alpha_pll - phase locked loop (PLL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) * @offset: base address of registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) * @vco_table: array of VCO settings
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) * @regs: alpha pll register map (see @clk_alpha_pll_regs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) * @clkr: regmap clock handle
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) struct clk_alpha_pll {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) u32 offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) const u8 *regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) const struct pll_vco *vco_table;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) size_t num_vco;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define SUPPORTS_OFFLINE_REQ BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define SUPPORTS_FSM_MODE BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define SUPPORTS_DYNAMIC_UPDATE BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) u8 flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) struct clk_regmap clkr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) * struct clk_alpha_pll_postdiv - phase locked loop (PLL) post-divider
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) * @offset: base address of registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) * @regs: alpha pll register map (see @clk_alpha_pll_regs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) * @width: width of post-divider
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) * @post_div_shift: shift to differentiate between odd & even post-divider
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) * @post_div_table: table with PLL odd and even post-divider settings
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) * @num_post_div: Number of PLL post-divider settings
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) * @clkr: regmap clock handle
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) struct clk_alpha_pll_postdiv {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) u32 offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) u8 width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) const u8 *regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) struct clk_regmap clkr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) int post_div_shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) const struct clk_div_table *post_div_table;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) size_t num_post_div;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) struct alpha_pll_config {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) u32 l;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) u32 alpha;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) u32 alpha_hi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) u32 config_ctl_val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) u32 config_ctl_hi_val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) u32 config_ctl_hi1_val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) u32 user_ctl_val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) u32 user_ctl_hi_val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) u32 user_ctl_hi1_val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) u32 test_ctl_val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) u32 test_ctl_hi_val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) u32 test_ctl_hi1_val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) u32 main_output_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) u32 aux_output_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) u32 aux2_output_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) u32 early_output_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) u32 alpha_en_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) u32 alpha_mode_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) u32 pre_div_val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) u32 pre_div_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) u32 post_div_val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) u32 post_div_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) u32 vco_val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) u32 vco_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) extern const struct clk_ops clk_alpha_pll_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) extern const struct clk_ops clk_alpha_pll_fixed_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) extern const struct clk_ops clk_alpha_pll_hwfsm_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) extern const struct clk_ops clk_alpha_pll_postdiv_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) extern const struct clk_ops clk_alpha_pll_huayra_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) extern const struct clk_ops clk_alpha_pll_postdiv_ro_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) extern const struct clk_ops clk_alpha_pll_fabia_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) extern const struct clk_ops clk_alpha_pll_fixed_fabia_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) extern const struct clk_ops clk_alpha_pll_postdiv_fabia_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) extern const struct clk_ops clk_alpha_pll_trion_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) extern const struct clk_ops clk_alpha_pll_fixed_trion_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) extern const struct clk_ops clk_alpha_pll_postdiv_trion_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) extern const struct clk_ops clk_alpha_pll_lucid_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define clk_alpha_pll_fixed_lucid_ops clk_alpha_pll_fixed_trion_ops
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) extern const struct clk_ops clk_alpha_pll_postdiv_lucid_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) void clk_alpha_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) const struct alpha_pll_config *config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) void clk_fabia_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) const struct alpha_pll_config *config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) void clk_trion_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) const struct alpha_pll_config *config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) #define clk_lucid_pll_configure(pll, regmap, config) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) clk_trion_pll_configure(pll, regmap, config)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) #endif
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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