^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (c) 2018, The Linux Foundation. All rights reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) #include <linux/clk-provider.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/regmap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <dt-bindings/clock/qcom,camcc-sdm845.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include "common.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include "clk-alpha-pll.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include "clk-branch.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include "clk-rcg.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include "clk-regmap.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include "gdsc.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) P_BI_TCXO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) P_CAM_CC_PLL0_OUT_EVEN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) P_CAM_CC_PLL1_OUT_EVEN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) P_CAM_CC_PLL2_OUT_EVEN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) P_CAM_CC_PLL3_OUT_EVEN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) P_CORE_BI_PLL_TEST_SE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) static const struct parent_map cam_cc_parent_map_0[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) { P_BI_TCXO, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) { P_CAM_CC_PLL2_OUT_EVEN, 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) { P_CAM_CC_PLL1_OUT_EVEN, 2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) { P_CAM_CC_PLL3_OUT_EVEN, 5 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) { P_CAM_CC_PLL0_OUT_EVEN, 6 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) { P_CORE_BI_PLL_TEST_SE, 7 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) static const char * const cam_cc_parent_names_0[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) "bi_tcxo",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) "cam_cc_pll2_out_even",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) "cam_cc_pll1_out_even",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) "cam_cc_pll3_out_even",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) "cam_cc_pll0_out_even",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) "core_bi_pll_test_se",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) static struct clk_alpha_pll cam_cc_pll0 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) .offset = 0x0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) .name = "cam_cc_pll0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) .parent_names = (const char *[]){ "bi_tcxo" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) .ops = &clk_alpha_pll_fabia_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) static const struct clk_div_table post_div_table_fabia_even[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) { 0x0, 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) { 0x1, 2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) static struct clk_alpha_pll_postdiv cam_cc_pll0_out_even = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) .offset = 0x0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) .post_div_shift = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) .post_div_table = post_div_table_fabia_even,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) .num_post_div = ARRAY_SIZE(post_div_table_fabia_even),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) .width = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) .name = "cam_cc_pll0_out_even",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) .parent_names = (const char *[]){ "cam_cc_pll0" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) .ops = &clk_alpha_pll_postdiv_fabia_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) static struct clk_alpha_pll cam_cc_pll1 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) .offset = 0x1000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) .name = "cam_cc_pll1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) .parent_names = (const char *[]){ "bi_tcxo" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) .ops = &clk_alpha_pll_fabia_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) static struct clk_alpha_pll_postdiv cam_cc_pll1_out_even = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) .offset = 0x1000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) .post_div_shift = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) .post_div_table = post_div_table_fabia_even,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) .num_post_div = ARRAY_SIZE(post_div_table_fabia_even),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) .width = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) .name = "cam_cc_pll1_out_even",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) .parent_names = (const char *[]){ "cam_cc_pll1" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) .ops = &clk_alpha_pll_postdiv_fabia_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) static struct clk_alpha_pll cam_cc_pll2 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) .offset = 0x2000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) .name = "cam_cc_pll2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) .parent_names = (const char *[]){ "bi_tcxo" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) .ops = &clk_alpha_pll_fabia_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) static struct clk_alpha_pll_postdiv cam_cc_pll2_out_even = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) .offset = 0x2000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) .post_div_shift = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) .post_div_table = post_div_table_fabia_even,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) .num_post_div = ARRAY_SIZE(post_div_table_fabia_even),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) .width = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) .name = "cam_cc_pll2_out_even",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) .parent_names = (const char *[]){ "cam_cc_pll2" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) .ops = &clk_alpha_pll_postdiv_fabia_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) static struct clk_alpha_pll cam_cc_pll3 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) .offset = 0x3000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) .name = "cam_cc_pll3",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) .parent_names = (const char *[]){ "bi_tcxo" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) .ops = &clk_alpha_pll_fabia_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) static struct clk_alpha_pll_postdiv cam_cc_pll3_out_even = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) .offset = 0x3000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) .post_div_shift = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) .post_div_table = post_div_table_fabia_even,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) .num_post_div = ARRAY_SIZE(post_div_table_fabia_even),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) .width = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) .name = "cam_cc_pll3_out_even",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) .parent_names = (const char *[]){ "cam_cc_pll3" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) .ops = &clk_alpha_pll_postdiv_fabia_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) static const struct freq_tbl ftbl_cam_cc_bps_clk_src[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) F(19200000, P_BI_TCXO, 1, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) F(100000000, P_CAM_CC_PLL0_OUT_EVEN, 6, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) F(200000000, P_CAM_CC_PLL0_OUT_EVEN, 3, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) F(404000000, P_CAM_CC_PLL1_OUT_EVEN, 2, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) F(480000000, P_CAM_CC_PLL2_OUT_EVEN, 1, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) F(600000000, P_CAM_CC_PLL0_OUT_EVEN, 1, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) * As per HW design, some of the CAMCC RCGs needs to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) * move to XO clock during their clock disable so using
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) * clk_rcg2_shared_ops for such RCGs. This is required
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) * to power down the camera memories gracefully.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) * Also, use CLK_SET_RATE_PARENT flag for the RCGs which
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) * have CAM_CC_PLL2_OUT_EVEN PLL as parent in frequency
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) * table and requires reconfiguration of the PLL frequency.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) static struct clk_rcg2 cam_cc_bps_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) .cmd_rcgr = 0x600c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) .mnd_width = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) .parent_map = cam_cc_parent_map_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) .freq_tbl = ftbl_cam_cc_bps_clk_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) .name = "cam_cc_bps_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) .parent_names = cam_cc_parent_names_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) .num_parents = 6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) .ops = &clk_rcg2_shared_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) static const struct freq_tbl ftbl_cam_cc_cci_clk_src[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) F(19200000, P_BI_TCXO, 1, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) F(37500000, P_CAM_CC_PLL0_OUT_EVEN, 16, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) F(50000000, P_CAM_CC_PLL0_OUT_EVEN, 12, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) F(100000000, P_CAM_CC_PLL0_OUT_EVEN, 6, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) static struct clk_rcg2 cam_cc_cci_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) .cmd_rcgr = 0xb0d8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) .mnd_width = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) .parent_map = cam_cc_parent_map_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) .freq_tbl = ftbl_cam_cc_cci_clk_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) .name = "cam_cc_cci_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) .parent_names = cam_cc_parent_names_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) .num_parents = 6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) static const struct freq_tbl ftbl_cam_cc_cphy_rx_clk_src[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) F(19200000, P_BI_TCXO, 1, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) F(384000000, P_CAM_CC_PLL3_OUT_EVEN, 1, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) static struct clk_rcg2 cam_cc_cphy_rx_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) .cmd_rcgr = 0x9060,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) .mnd_width = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) .parent_map = cam_cc_parent_map_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) .freq_tbl = ftbl_cam_cc_cphy_rx_clk_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) .name = "cam_cc_cphy_rx_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) .parent_names = cam_cc_parent_names_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) .num_parents = 6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) static const struct freq_tbl ftbl_cam_cc_csi0phytimer_clk_src[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) F(19200000, P_BI_TCXO, 1, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) F(240000000, P_CAM_CC_PLL2_OUT_EVEN, 2, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) F(269333333, P_CAM_CC_PLL1_OUT_EVEN, 3, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) static struct clk_rcg2 cam_cc_csi0phytimer_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) .cmd_rcgr = 0x5004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) .mnd_width = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) .parent_map = cam_cc_parent_map_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) .freq_tbl = ftbl_cam_cc_csi0phytimer_clk_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) .name = "cam_cc_csi0phytimer_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) .parent_names = cam_cc_parent_names_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) .num_parents = 6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) static struct clk_rcg2 cam_cc_csi1phytimer_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) .cmd_rcgr = 0x5028,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) .mnd_width = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) .parent_map = cam_cc_parent_map_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) .freq_tbl = ftbl_cam_cc_csi0phytimer_clk_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) .name = "cam_cc_csi1phytimer_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) .parent_names = cam_cc_parent_names_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) .num_parents = 6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) static struct clk_rcg2 cam_cc_csi2phytimer_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) .cmd_rcgr = 0x504c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) .mnd_width = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) .parent_map = cam_cc_parent_map_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) .freq_tbl = ftbl_cam_cc_csi0phytimer_clk_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) .name = "cam_cc_csi2phytimer_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) .parent_names = cam_cc_parent_names_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) .num_parents = 6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) static struct clk_rcg2 cam_cc_csi3phytimer_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) .cmd_rcgr = 0x5070,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) .mnd_width = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) .parent_map = cam_cc_parent_map_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) .freq_tbl = ftbl_cam_cc_csi0phytimer_clk_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) .name = "cam_cc_csi3phytimer_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) .parent_names = cam_cc_parent_names_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) .num_parents = 6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) static const struct freq_tbl ftbl_cam_cc_fast_ahb_clk_src[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) F(19200000, P_BI_TCXO, 1, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) F(50000000, P_CAM_CC_PLL0_OUT_EVEN, 12, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) F(100000000, P_CAM_CC_PLL0_OUT_EVEN, 6, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) F(200000000, P_CAM_CC_PLL0_OUT_EVEN, 3, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) F(300000000, P_CAM_CC_PLL0_OUT_EVEN, 2, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) F(400000000, P_CAM_CC_PLL0_OUT_EVEN, 1.5, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) static struct clk_rcg2 cam_cc_fast_ahb_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) .cmd_rcgr = 0x6038,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) .mnd_width = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) .parent_map = cam_cc_parent_map_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) .freq_tbl = ftbl_cam_cc_fast_ahb_clk_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) .name = "cam_cc_fast_ahb_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) .parent_names = cam_cc_parent_names_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) .num_parents = 6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) static const struct freq_tbl ftbl_cam_cc_fd_core_clk_src[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) F(19200000, P_BI_TCXO, 1, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) F(384000000, P_CAM_CC_PLL3_OUT_EVEN, 1, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) F(400000000, P_CAM_CC_PLL0_OUT_EVEN, 1.5, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) F(538666667, P_CAM_CC_PLL1_OUT_EVEN, 1.5, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) F(600000000, P_CAM_CC_PLL0_OUT_EVEN, 1, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) static struct clk_rcg2 cam_cc_fd_core_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) .cmd_rcgr = 0xb0b0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) .mnd_width = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) .parent_map = cam_cc_parent_map_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) .freq_tbl = ftbl_cam_cc_fd_core_clk_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) .name = "cam_cc_fd_core_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) .parent_names = cam_cc_parent_names_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) .num_parents = 6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) .ops = &clk_rcg2_shared_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) static const struct freq_tbl ftbl_cam_cc_icp_clk_src[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) F(19200000, P_BI_TCXO, 1, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) F(384000000, P_CAM_CC_PLL3_OUT_EVEN, 1, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) F(400000000, P_CAM_CC_PLL0_OUT_EVEN, 1.5, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) F(538666667, P_CAM_CC_PLL1_OUT_EVEN, 1.5, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) F(600000000, P_CAM_CC_PLL0_OUT_EVEN, 1, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) static struct clk_rcg2 cam_cc_icp_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) .cmd_rcgr = 0xb088,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) .mnd_width = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) .parent_map = cam_cc_parent_map_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) .freq_tbl = ftbl_cam_cc_icp_clk_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) .name = "cam_cc_icp_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) .parent_names = cam_cc_parent_names_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) .num_parents = 6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) .ops = &clk_rcg2_shared_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) static const struct freq_tbl ftbl_cam_cc_ife_0_clk_src[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) F(19200000, P_BI_TCXO, 1, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) F(100000000, P_CAM_CC_PLL0_OUT_EVEN, 6, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) F(320000000, P_CAM_CC_PLL2_OUT_EVEN, 1.5, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) F(404000000, P_CAM_CC_PLL1_OUT_EVEN, 2, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) F(480000000, P_CAM_CC_PLL2_OUT_EVEN, 1, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) F(600000000, P_CAM_CC_PLL0_OUT_EVEN, 1, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) static struct clk_rcg2 cam_cc_ife_0_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) .cmd_rcgr = 0x900c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) .mnd_width = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) .parent_map = cam_cc_parent_map_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) .freq_tbl = ftbl_cam_cc_ife_0_clk_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) .name = "cam_cc_ife_0_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) .parent_names = cam_cc_parent_names_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) .num_parents = 6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) .ops = &clk_rcg2_shared_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) static const struct freq_tbl ftbl_cam_cc_ife_0_csid_clk_src[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) F(19200000, P_BI_TCXO, 1, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) F(75000000, P_CAM_CC_PLL0_OUT_EVEN, 8, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) F(384000000, P_CAM_CC_PLL3_OUT_EVEN, 1, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) F(538666667, P_CAM_CC_PLL1_OUT_EVEN, 1.5, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) static struct clk_rcg2 cam_cc_ife_0_csid_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) .cmd_rcgr = 0x9038,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) .mnd_width = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) .parent_map = cam_cc_parent_map_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) .freq_tbl = ftbl_cam_cc_ife_0_csid_clk_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) .name = "cam_cc_ife_0_csid_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) .parent_names = cam_cc_parent_names_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) .num_parents = 6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) .ops = &clk_rcg2_shared_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) static struct clk_rcg2 cam_cc_ife_1_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) .cmd_rcgr = 0xa00c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) .mnd_width = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) .parent_map = cam_cc_parent_map_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) .freq_tbl = ftbl_cam_cc_ife_0_clk_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) .name = "cam_cc_ife_1_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) .parent_names = cam_cc_parent_names_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) .num_parents = 6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) .ops = &clk_rcg2_shared_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) static struct clk_rcg2 cam_cc_ife_1_csid_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) .cmd_rcgr = 0xa030,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) .mnd_width = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) .parent_map = cam_cc_parent_map_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) .freq_tbl = ftbl_cam_cc_ife_0_csid_clk_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) .name = "cam_cc_ife_1_csid_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) .parent_names = cam_cc_parent_names_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) .num_parents = 6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) .ops = &clk_rcg2_shared_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) static struct clk_rcg2 cam_cc_ife_lite_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) .cmd_rcgr = 0xb004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) .mnd_width = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) .parent_map = cam_cc_parent_map_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) .freq_tbl = ftbl_cam_cc_ife_0_clk_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) .name = "cam_cc_ife_lite_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) .parent_names = cam_cc_parent_names_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) .num_parents = 6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) .ops = &clk_rcg2_shared_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) static struct clk_rcg2 cam_cc_ife_lite_csid_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) .cmd_rcgr = 0xb024,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) .mnd_width = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) .parent_map = cam_cc_parent_map_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) .freq_tbl = ftbl_cam_cc_ife_0_csid_clk_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) .name = "cam_cc_ife_lite_csid_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) .parent_names = cam_cc_parent_names_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) .num_parents = 6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) .ops = &clk_rcg2_shared_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) static const struct freq_tbl ftbl_cam_cc_ipe_0_clk_src[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) F(19200000, P_BI_TCXO, 1, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) F(100000000, P_CAM_CC_PLL0_OUT_EVEN, 6, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) F(240000000, P_CAM_CC_PLL0_OUT_EVEN, 2.5, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) F(404000000, P_CAM_CC_PLL1_OUT_EVEN, 2, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) F(480000000, P_CAM_CC_PLL2_OUT_EVEN, 1, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) F(538666667, P_CAM_CC_PLL1_OUT_EVEN, 1.5, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) F(600000000, P_CAM_CC_PLL0_OUT_EVEN, 1, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) static struct clk_rcg2 cam_cc_ipe_0_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) .cmd_rcgr = 0x700c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) .mnd_width = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) .parent_map = cam_cc_parent_map_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) .freq_tbl = ftbl_cam_cc_ipe_0_clk_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) .name = "cam_cc_ipe_0_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) .parent_names = cam_cc_parent_names_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) .num_parents = 6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) .ops = &clk_rcg2_shared_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) static struct clk_rcg2 cam_cc_ipe_1_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) .cmd_rcgr = 0x800c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) .mnd_width = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) .parent_map = cam_cc_parent_map_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) .freq_tbl = ftbl_cam_cc_ipe_0_clk_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) .name = "cam_cc_ipe_1_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) .parent_names = cam_cc_parent_names_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) .num_parents = 6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) .ops = &clk_rcg2_shared_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) static struct clk_rcg2 cam_cc_jpeg_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) .cmd_rcgr = 0xb04c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) .mnd_width = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) .parent_map = cam_cc_parent_map_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) .freq_tbl = ftbl_cam_cc_bps_clk_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) .name = "cam_cc_jpeg_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) .parent_names = cam_cc_parent_names_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) .num_parents = 6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) .ops = &clk_rcg2_shared_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) static const struct freq_tbl ftbl_cam_cc_lrme_clk_src[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) F(19200000, P_BI_TCXO, 1, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) F(100000000, P_CAM_CC_PLL0_OUT_EVEN, 6, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) F(200000000, P_CAM_CC_PLL0_OUT_EVEN, 3, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) F(269333333, P_CAM_CC_PLL1_OUT_EVEN, 3, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) F(320000000, P_CAM_CC_PLL2_OUT_EVEN, 1.5, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) F(400000000, P_CAM_CC_PLL0_OUT_EVEN, 1.5, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) static struct clk_rcg2 cam_cc_lrme_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) .cmd_rcgr = 0xb0f8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) .mnd_width = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) .parent_map = cam_cc_parent_map_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) .freq_tbl = ftbl_cam_cc_lrme_clk_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) .name = "cam_cc_lrme_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) .parent_names = cam_cc_parent_names_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) .num_parents = 6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) .ops = &clk_rcg2_shared_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) static const struct freq_tbl ftbl_cam_cc_mclk0_clk_src[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) F(19200000, P_BI_TCXO, 1, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) F(24000000, P_CAM_CC_PLL2_OUT_EVEN, 10, 1, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) F(33333333, P_CAM_CC_PLL0_OUT_EVEN, 2, 1, 9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) F(34285714, P_CAM_CC_PLL2_OUT_EVEN, 14, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) static struct clk_rcg2 cam_cc_mclk0_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) .cmd_rcgr = 0x4004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) .mnd_width = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) .parent_map = cam_cc_parent_map_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) .freq_tbl = ftbl_cam_cc_mclk0_clk_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) .name = "cam_cc_mclk0_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) .parent_names = cam_cc_parent_names_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) .num_parents = 6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) static struct clk_rcg2 cam_cc_mclk1_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) .cmd_rcgr = 0x4024,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) .mnd_width = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) .parent_map = cam_cc_parent_map_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) .freq_tbl = ftbl_cam_cc_mclk0_clk_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) .name = "cam_cc_mclk1_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) .parent_names = cam_cc_parent_names_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) .num_parents = 6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) static struct clk_rcg2 cam_cc_mclk2_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) .cmd_rcgr = 0x4044,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) .mnd_width = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) .parent_map = cam_cc_parent_map_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) .freq_tbl = ftbl_cam_cc_mclk0_clk_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) .name = "cam_cc_mclk2_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) .parent_names = cam_cc_parent_names_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) .num_parents = 6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) static struct clk_rcg2 cam_cc_mclk3_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) .cmd_rcgr = 0x4064,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) .mnd_width = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) .parent_map = cam_cc_parent_map_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) .freq_tbl = ftbl_cam_cc_mclk0_clk_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) .name = "cam_cc_mclk3_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) .parent_names = cam_cc_parent_names_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) .num_parents = 6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) static const struct freq_tbl ftbl_cam_cc_slow_ahb_clk_src[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) F(19200000, P_BI_TCXO, 1, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) F(60000000, P_CAM_CC_PLL0_OUT_EVEN, 10, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) F(66666667, P_CAM_CC_PLL0_OUT_EVEN, 9, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) F(73846154, P_CAM_CC_PLL2_OUT_EVEN, 6.5, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) F(80000000, P_CAM_CC_PLL2_OUT_EVEN, 6, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) static struct clk_rcg2 cam_cc_slow_ahb_clk_src = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) .cmd_rcgr = 0x6054,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) .mnd_width = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) .hid_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) .parent_map = cam_cc_parent_map_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) .freq_tbl = ftbl_cam_cc_slow_ahb_clk_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) .clkr.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) .name = "cam_cc_slow_ahb_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) .parent_names = cam_cc_parent_names_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) .num_parents = 6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) .ops = &clk_rcg2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) static struct clk_branch cam_cc_bps_ahb_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) .halt_reg = 0x606c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) .halt_check = BRANCH_HALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) .enable_reg = 0x606c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) .name = "cam_cc_bps_ahb_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) "cam_cc_slow_ahb_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) static struct clk_branch cam_cc_bps_areg_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) .halt_reg = 0x6050,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) .halt_check = BRANCH_HALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) .enable_reg = 0x6050,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) .name = "cam_cc_bps_areg_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) "cam_cc_fast_ahb_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) static struct clk_branch cam_cc_bps_axi_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) .halt_reg = 0x6034,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) .halt_check = BRANCH_HALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) .enable_reg = 0x6034,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) .name = "cam_cc_bps_axi_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) static struct clk_branch cam_cc_bps_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) .halt_reg = 0x6024,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) .halt_check = BRANCH_HALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) .enable_reg = 0x6024,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) .name = "cam_cc_bps_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) "cam_cc_bps_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) static struct clk_branch cam_cc_camnoc_atb_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) .halt_reg = 0xb12c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) .halt_check = BRANCH_HALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) .enable_reg = 0xb12c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) .name = "cam_cc_camnoc_atb_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) static struct clk_branch cam_cc_camnoc_axi_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) .halt_reg = 0xb124,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) .halt_check = BRANCH_HALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) .enable_reg = 0xb124,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) .name = "cam_cc_camnoc_axi_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) static struct clk_branch cam_cc_cci_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) .halt_reg = 0xb0f0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) .halt_check = BRANCH_HALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) .enable_reg = 0xb0f0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) .name = "cam_cc_cci_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) "cam_cc_cci_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) static struct clk_branch cam_cc_cpas_ahb_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) .halt_reg = 0xb11c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) .halt_check = BRANCH_HALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) .enable_reg = 0xb11c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) .name = "cam_cc_cpas_ahb_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) "cam_cc_slow_ahb_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) static struct clk_branch cam_cc_csi0phytimer_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) .halt_reg = 0x501c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) .halt_check = BRANCH_HALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) .enable_reg = 0x501c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) .name = "cam_cc_csi0phytimer_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) "cam_cc_csi0phytimer_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) static struct clk_branch cam_cc_csi1phytimer_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) .halt_reg = 0x5040,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) .halt_check = BRANCH_HALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) .enable_reg = 0x5040,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) .name = "cam_cc_csi1phytimer_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) "cam_cc_csi1phytimer_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) static struct clk_branch cam_cc_csi2phytimer_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) .halt_reg = 0x5064,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) .halt_check = BRANCH_HALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) .enable_reg = 0x5064,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) .name = "cam_cc_csi2phytimer_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) "cam_cc_csi2phytimer_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) static struct clk_branch cam_cc_csi3phytimer_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) .halt_reg = 0x5088,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) .halt_check = BRANCH_HALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) .enable_reg = 0x5088,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) .name = "cam_cc_csi3phytimer_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) "cam_cc_csi3phytimer_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) static struct clk_branch cam_cc_csiphy0_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) .halt_reg = 0x5020,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) .halt_check = BRANCH_HALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) .enable_reg = 0x5020,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) .name = "cam_cc_csiphy0_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) "cam_cc_cphy_rx_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) static struct clk_branch cam_cc_csiphy1_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) .halt_reg = 0x5044,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) .halt_check = BRANCH_HALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) .enable_reg = 0x5044,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) .name = "cam_cc_csiphy1_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) "cam_cc_cphy_rx_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) static struct clk_branch cam_cc_csiphy2_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) .halt_reg = 0x5068,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) .halt_check = BRANCH_HALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) .enable_reg = 0x5068,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) .name = "cam_cc_csiphy2_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) "cam_cc_cphy_rx_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) static struct clk_branch cam_cc_csiphy3_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) .halt_reg = 0x508c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) .halt_check = BRANCH_HALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) .enable_reg = 0x508c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) .name = "cam_cc_csiphy3_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) "cam_cc_cphy_rx_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) static struct clk_branch cam_cc_fd_core_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) .halt_reg = 0xb0c8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) .halt_check = BRANCH_HALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) .enable_reg = 0xb0c8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) .name = "cam_cc_fd_core_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) "cam_cc_fd_core_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) static struct clk_branch cam_cc_fd_core_uar_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) .halt_reg = 0xb0d0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) .halt_check = BRANCH_HALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) .enable_reg = 0xb0d0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) .name = "cam_cc_fd_core_uar_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) "cam_cc_fd_core_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) static struct clk_branch cam_cc_icp_apb_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) .halt_reg = 0xb084,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) .halt_check = BRANCH_HALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) .enable_reg = 0xb084,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) .name = "cam_cc_icp_apb_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) static struct clk_branch cam_cc_icp_atb_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) .halt_reg = 0xb078,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) .halt_check = BRANCH_HALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) .enable_reg = 0xb078,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) .name = "cam_cc_icp_atb_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) static struct clk_branch cam_cc_icp_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) .halt_reg = 0xb0a0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) .halt_check = BRANCH_HALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) .enable_reg = 0xb0a0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) .name = "cam_cc_icp_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) "cam_cc_icp_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) static struct clk_branch cam_cc_icp_cti_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) .halt_reg = 0xb07c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) .halt_check = BRANCH_HALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) .enable_reg = 0xb07c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) .name = "cam_cc_icp_cti_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) static struct clk_branch cam_cc_icp_ts_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) .halt_reg = 0xb080,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) .halt_check = BRANCH_HALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) .enable_reg = 0xb080,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) .name = "cam_cc_icp_ts_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) static struct clk_branch cam_cc_ife_0_axi_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) .halt_reg = 0x907c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) .halt_check = BRANCH_HALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) .enable_reg = 0x907c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) .name = "cam_cc_ife_0_axi_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) static struct clk_branch cam_cc_ife_0_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) .halt_reg = 0x9024,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) .halt_check = BRANCH_HALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) .enable_reg = 0x9024,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) .name = "cam_cc_ife_0_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) "cam_cc_ife_0_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) static struct clk_branch cam_cc_ife_0_cphy_rx_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) .halt_reg = 0x9078,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) .halt_check = BRANCH_HALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) .enable_reg = 0x9078,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) .name = "cam_cc_ife_0_cphy_rx_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) "cam_cc_cphy_rx_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) static struct clk_branch cam_cc_ife_0_csid_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) .halt_reg = 0x9050,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) .halt_check = BRANCH_HALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) .enable_reg = 0x9050,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090) .name = "cam_cc_ife_0_csid_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) "cam_cc_ife_0_csid_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) static struct clk_branch cam_cc_ife_0_dsp_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) .halt_reg = 0x9034,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103) .halt_check = BRANCH_HALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) .enable_reg = 0x9034,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) .name = "cam_cc_ife_0_dsp_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) "cam_cc_ife_0_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118) static struct clk_branch cam_cc_ife_1_axi_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119) .halt_reg = 0xa054,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120) .halt_check = BRANCH_HALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122) .enable_reg = 0xa054,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125) .name = "cam_cc_ife_1_axi_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131) static struct clk_branch cam_cc_ife_1_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132) .halt_reg = 0xa024,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133) .halt_check = BRANCH_HALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135) .enable_reg = 0xa024,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138) .name = "cam_cc_ife_1_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140) "cam_cc_ife_1_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149) static struct clk_branch cam_cc_ife_1_cphy_rx_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150) .halt_reg = 0xa050,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151) .halt_check = BRANCH_HALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153) .enable_reg = 0xa050,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156) .name = "cam_cc_ife_1_cphy_rx_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158) "cam_cc_cphy_rx_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167) static struct clk_branch cam_cc_ife_1_csid_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168) .halt_reg = 0xa048,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169) .halt_check = BRANCH_HALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171) .enable_reg = 0xa048,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174) .name = "cam_cc_ife_1_csid_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176) "cam_cc_ife_1_csid_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185) static struct clk_branch cam_cc_ife_1_dsp_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186) .halt_reg = 0xa02c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187) .halt_check = BRANCH_HALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189) .enable_reg = 0xa02c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192) .name = "cam_cc_ife_1_dsp_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194) "cam_cc_ife_1_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202) static struct clk_branch cam_cc_ife_lite_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203) .halt_reg = 0xb01c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204) .halt_check = BRANCH_HALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206) .enable_reg = 0xb01c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209) .name = "cam_cc_ife_lite_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211) "cam_cc_ife_lite_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220) static struct clk_branch cam_cc_ife_lite_cphy_rx_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221) .halt_reg = 0xb044,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222) .halt_check = BRANCH_HALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224) .enable_reg = 0xb044,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227) .name = "cam_cc_ife_lite_cphy_rx_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229) "cam_cc_cphy_rx_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238) static struct clk_branch cam_cc_ife_lite_csid_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239) .halt_reg = 0xb03c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240) .halt_check = BRANCH_HALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242) .enable_reg = 0xb03c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245) .name = "cam_cc_ife_lite_csid_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247) "cam_cc_ife_lite_csid_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1248) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1249) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1250) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1251) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1252) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1253) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1254) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1255)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1256) static struct clk_branch cam_cc_ipe_0_ahb_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1257) .halt_reg = 0x703c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1258) .halt_check = BRANCH_HALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1259) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1260) .enable_reg = 0x703c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1261) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1262) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1263) .name = "cam_cc_ipe_0_ahb_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1264) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1265) "cam_cc_slow_ahb_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1266) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1267) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1268) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1269) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1270) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1271) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1272) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1273)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1274) static struct clk_branch cam_cc_ipe_0_areg_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1275) .halt_reg = 0x7038,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1276) .halt_check = BRANCH_HALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1277) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1278) .enable_reg = 0x7038,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1279) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1280) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1281) .name = "cam_cc_ipe_0_areg_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1282) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1283) "cam_cc_fast_ahb_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1284) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1285) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1286) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1287) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1288) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1289) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1290) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1291)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1292) static struct clk_branch cam_cc_ipe_0_axi_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1293) .halt_reg = 0x7034,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1294) .halt_check = BRANCH_HALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1295) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1296) .enable_reg = 0x7034,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1297) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1298) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1299) .name = "cam_cc_ipe_0_axi_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1300) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1301) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1302) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1303) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1304)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1305) static struct clk_branch cam_cc_ipe_0_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1306) .halt_reg = 0x7024,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1307) .halt_check = BRANCH_HALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1308) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1309) .enable_reg = 0x7024,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1310) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1311) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1312) .name = "cam_cc_ipe_0_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1313) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1314) "cam_cc_ipe_0_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1315) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1316) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1317) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1318) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1319) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1320) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1321) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1322)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1323) static struct clk_branch cam_cc_ipe_1_ahb_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1324) .halt_reg = 0x803c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1325) .halt_check = BRANCH_HALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1326) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1327) .enable_reg = 0x803c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1328) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1329) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1330) .name = "cam_cc_ipe_1_ahb_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1331) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1332) "cam_cc_slow_ahb_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1333) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1334) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1335) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1336) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1337) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1338) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1339) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1340)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1341) static struct clk_branch cam_cc_ipe_1_areg_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1342) .halt_reg = 0x8038,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1343) .halt_check = BRANCH_HALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1344) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1345) .enable_reg = 0x8038,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1346) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1347) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1348) .name = "cam_cc_ipe_1_areg_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1349) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1350) "cam_cc_fast_ahb_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1351) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1352) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1353) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1354) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1355) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1356) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1357) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1358)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1359) static struct clk_branch cam_cc_ipe_1_axi_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1360) .halt_reg = 0x8034,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1361) .halt_check = BRANCH_HALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1362) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1363) .enable_reg = 0x8034,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1364) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1365) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1366) .name = "cam_cc_ipe_1_axi_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1367) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1368) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1369) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1370) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1371)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1372) static struct clk_branch cam_cc_ipe_1_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1373) .halt_reg = 0x8024,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1374) .halt_check = BRANCH_HALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1375) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1376) .enable_reg = 0x8024,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1377) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1378) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1379) .name = "cam_cc_ipe_1_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1380) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1381) "cam_cc_ipe_1_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1382) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1383) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1384) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1385) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1386) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1387) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1388) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1389)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1390) static struct clk_branch cam_cc_jpeg_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1391) .halt_reg = 0xb064,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1392) .halt_check = BRANCH_HALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1393) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1394) .enable_reg = 0xb064,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1395) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1396) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1397) .name = "cam_cc_jpeg_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1398) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1399) "cam_cc_jpeg_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1400) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1401) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1402) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1403) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1404) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1405) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1406) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1407)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1408) static struct clk_branch cam_cc_lrme_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1409) .halt_reg = 0xb110,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1410) .halt_check = BRANCH_HALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1411) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1412) .enable_reg = 0xb110,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1413) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1414) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1415) .name = "cam_cc_lrme_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1416) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1417) "cam_cc_lrme_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1418) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1419) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1420) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1421) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1422) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1423) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1424) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1425)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1426) static struct clk_branch cam_cc_mclk0_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1427) .halt_reg = 0x401c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1428) .halt_check = BRANCH_HALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1429) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1430) .enable_reg = 0x401c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1431) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1432) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1433) .name = "cam_cc_mclk0_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1434) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1435) "cam_cc_mclk0_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1436) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1437) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1438) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1439) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1440) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1441) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1442) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1443)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1444) static struct clk_branch cam_cc_mclk1_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1445) .halt_reg = 0x403c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1446) .halt_check = BRANCH_HALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1447) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1448) .enable_reg = 0x403c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1449) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1450) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1451) .name = "cam_cc_mclk1_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1452) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1453) "cam_cc_mclk1_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1454) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1455) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1456) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1457) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1458) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1459) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1460) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1461)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1462) static struct clk_branch cam_cc_mclk2_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1463) .halt_reg = 0x405c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1464) .halt_check = BRANCH_HALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1465) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1466) .enable_reg = 0x405c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1467) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1468) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1469) .name = "cam_cc_mclk2_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1470) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1471) "cam_cc_mclk2_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1472) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1473) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1474) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1475) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1476) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1477) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1478) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1479)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1480) static struct clk_branch cam_cc_mclk3_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1481) .halt_reg = 0x407c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1482) .halt_check = BRANCH_HALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1483) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1484) .enable_reg = 0x407c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1485) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1486) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1487) .name = "cam_cc_mclk3_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1488) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1489) "cam_cc_mclk3_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1490) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1491) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1492) .flags = CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1493) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1494) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1495) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1496) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1497)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1498) static struct clk_branch cam_cc_soc_ahb_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1499) .halt_reg = 0xb13c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1500) .halt_check = BRANCH_HALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1501) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1502) .enable_reg = 0xb13c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1503) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1504) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1505) .name = "cam_cc_soc_ahb_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1506) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1507) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1508) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1509) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1510)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1511) static struct clk_branch cam_cc_sys_tmr_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1512) .halt_reg = 0xb0a8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1513) .halt_check = BRANCH_HALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1514) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1515) .enable_reg = 0xb0a8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1516) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1517) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1518) .name = "cam_cc_sys_tmr_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1519) .ops = &clk_branch2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1520) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1521) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1522) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1523)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1524) static struct gdsc bps_gdsc = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1525) .gdscr = 0x6004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1526) .pd = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1527) .name = "bps_gdsc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1528) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1529) .flags = HW_CTRL | POLL_CFG_GDSCR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1530) .pwrsts = PWRSTS_OFF_ON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1531) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1532)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1533) static struct gdsc ipe_0_gdsc = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1534) .gdscr = 0x7004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1535) .pd = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1536) .name = "ipe_0_gdsc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1537) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1538) .flags = HW_CTRL | POLL_CFG_GDSCR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1539) .pwrsts = PWRSTS_OFF_ON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1540) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1541)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1542) static struct gdsc ipe_1_gdsc = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1543) .gdscr = 0x8004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1544) .pd = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1545) .name = "ipe_1_gdsc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1546) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1547) .flags = HW_CTRL | POLL_CFG_GDSCR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1548) .pwrsts = PWRSTS_OFF_ON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1549) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1550)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1551) static struct gdsc ife_0_gdsc = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1552) .gdscr = 0x9004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1553) .pd = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1554) .name = "ife_0_gdsc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1555) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1556) .flags = POLL_CFG_GDSCR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1557) .pwrsts = PWRSTS_OFF_ON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1558) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1559)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1560) static struct gdsc ife_1_gdsc = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1561) .gdscr = 0xa004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1562) .pd = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1563) .name = "ife_1_gdsc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1564) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1565) .flags = POLL_CFG_GDSCR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1566) .pwrsts = PWRSTS_OFF_ON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1567) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1568)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1569) static struct gdsc titan_top_gdsc = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1570) .gdscr = 0xb134,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1571) .pd = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1572) .name = "titan_top_gdsc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1573) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1574) .flags = POLL_CFG_GDSCR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1575) .pwrsts = PWRSTS_OFF_ON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1576) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1577)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1578) static struct clk_regmap *cam_cc_sdm845_clocks[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1579) [CAM_CC_BPS_AHB_CLK] = &cam_cc_bps_ahb_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1580) [CAM_CC_BPS_AREG_CLK] = &cam_cc_bps_areg_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1581) [CAM_CC_BPS_AXI_CLK] = &cam_cc_bps_axi_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1582) [CAM_CC_BPS_CLK] = &cam_cc_bps_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1583) [CAM_CC_BPS_CLK_SRC] = &cam_cc_bps_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1584) [CAM_CC_CAMNOC_ATB_CLK] = &cam_cc_camnoc_atb_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1585) [CAM_CC_CAMNOC_AXI_CLK] = &cam_cc_camnoc_axi_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1586) [CAM_CC_CCI_CLK] = &cam_cc_cci_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1587) [CAM_CC_CCI_CLK_SRC] = &cam_cc_cci_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1588) [CAM_CC_CPAS_AHB_CLK] = &cam_cc_cpas_ahb_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1589) [CAM_CC_CPHY_RX_CLK_SRC] = &cam_cc_cphy_rx_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1590) [CAM_CC_CSI0PHYTIMER_CLK] = &cam_cc_csi0phytimer_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1591) [CAM_CC_CSI0PHYTIMER_CLK_SRC] = &cam_cc_csi0phytimer_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1592) [CAM_CC_CSI1PHYTIMER_CLK] = &cam_cc_csi1phytimer_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1593) [CAM_CC_CSI1PHYTIMER_CLK_SRC] = &cam_cc_csi1phytimer_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1594) [CAM_CC_CSI2PHYTIMER_CLK] = &cam_cc_csi2phytimer_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1595) [CAM_CC_CSI2PHYTIMER_CLK_SRC] = &cam_cc_csi2phytimer_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1596) [CAM_CC_CSI3PHYTIMER_CLK] = &cam_cc_csi3phytimer_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1597) [CAM_CC_CSI3PHYTIMER_CLK_SRC] = &cam_cc_csi3phytimer_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1598) [CAM_CC_CSIPHY0_CLK] = &cam_cc_csiphy0_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1599) [CAM_CC_CSIPHY1_CLK] = &cam_cc_csiphy1_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1600) [CAM_CC_CSIPHY2_CLK] = &cam_cc_csiphy2_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1601) [CAM_CC_CSIPHY3_CLK] = &cam_cc_csiphy3_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1602) [CAM_CC_FAST_AHB_CLK_SRC] = &cam_cc_fast_ahb_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1603) [CAM_CC_FD_CORE_CLK] = &cam_cc_fd_core_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1604) [CAM_CC_FD_CORE_CLK_SRC] = &cam_cc_fd_core_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1605) [CAM_CC_FD_CORE_UAR_CLK] = &cam_cc_fd_core_uar_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1606) [CAM_CC_ICP_APB_CLK] = &cam_cc_icp_apb_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1607) [CAM_CC_ICP_ATB_CLK] = &cam_cc_icp_atb_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1608) [CAM_CC_ICP_CLK] = &cam_cc_icp_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1609) [CAM_CC_ICP_CLK_SRC] = &cam_cc_icp_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1610) [CAM_CC_ICP_CTI_CLK] = &cam_cc_icp_cti_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1611) [CAM_CC_ICP_TS_CLK] = &cam_cc_icp_ts_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1612) [CAM_CC_IFE_0_AXI_CLK] = &cam_cc_ife_0_axi_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1613) [CAM_CC_IFE_0_CLK] = &cam_cc_ife_0_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1614) [CAM_CC_IFE_0_CLK_SRC] = &cam_cc_ife_0_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1615) [CAM_CC_IFE_0_CPHY_RX_CLK] = &cam_cc_ife_0_cphy_rx_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1616) [CAM_CC_IFE_0_CSID_CLK] = &cam_cc_ife_0_csid_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1617) [CAM_CC_IFE_0_CSID_CLK_SRC] = &cam_cc_ife_0_csid_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1618) [CAM_CC_IFE_0_DSP_CLK] = &cam_cc_ife_0_dsp_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1619) [CAM_CC_IFE_1_AXI_CLK] = &cam_cc_ife_1_axi_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1620) [CAM_CC_IFE_1_CLK] = &cam_cc_ife_1_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1621) [CAM_CC_IFE_1_CLK_SRC] = &cam_cc_ife_1_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1622) [CAM_CC_IFE_1_CPHY_RX_CLK] = &cam_cc_ife_1_cphy_rx_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1623) [CAM_CC_IFE_1_CSID_CLK] = &cam_cc_ife_1_csid_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1624) [CAM_CC_IFE_1_CSID_CLK_SRC] = &cam_cc_ife_1_csid_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1625) [CAM_CC_IFE_1_DSP_CLK] = &cam_cc_ife_1_dsp_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1626) [CAM_CC_IFE_LITE_CLK] = &cam_cc_ife_lite_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1627) [CAM_CC_IFE_LITE_CLK_SRC] = &cam_cc_ife_lite_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1628) [CAM_CC_IFE_LITE_CPHY_RX_CLK] = &cam_cc_ife_lite_cphy_rx_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1629) [CAM_CC_IFE_LITE_CSID_CLK] = &cam_cc_ife_lite_csid_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1630) [CAM_CC_IFE_LITE_CSID_CLK_SRC] = &cam_cc_ife_lite_csid_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1631) [CAM_CC_IPE_0_AHB_CLK] = &cam_cc_ipe_0_ahb_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1632) [CAM_CC_IPE_0_AREG_CLK] = &cam_cc_ipe_0_areg_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1633) [CAM_CC_IPE_0_AXI_CLK] = &cam_cc_ipe_0_axi_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1634) [CAM_CC_IPE_0_CLK] = &cam_cc_ipe_0_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1635) [CAM_CC_IPE_0_CLK_SRC] = &cam_cc_ipe_0_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1636) [CAM_CC_IPE_1_AHB_CLK] = &cam_cc_ipe_1_ahb_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1637) [CAM_CC_IPE_1_AREG_CLK] = &cam_cc_ipe_1_areg_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1638) [CAM_CC_IPE_1_AXI_CLK] = &cam_cc_ipe_1_axi_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1639) [CAM_CC_IPE_1_CLK] = &cam_cc_ipe_1_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1640) [CAM_CC_IPE_1_CLK_SRC] = &cam_cc_ipe_1_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1641) [CAM_CC_JPEG_CLK] = &cam_cc_jpeg_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1642) [CAM_CC_JPEG_CLK_SRC] = &cam_cc_jpeg_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1643) [CAM_CC_LRME_CLK] = &cam_cc_lrme_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1644) [CAM_CC_LRME_CLK_SRC] = &cam_cc_lrme_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1645) [CAM_CC_MCLK0_CLK] = &cam_cc_mclk0_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1646) [CAM_CC_MCLK0_CLK_SRC] = &cam_cc_mclk0_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1647) [CAM_CC_MCLK1_CLK] = &cam_cc_mclk1_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1648) [CAM_CC_MCLK1_CLK_SRC] = &cam_cc_mclk1_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1649) [CAM_CC_MCLK2_CLK] = &cam_cc_mclk2_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1650) [CAM_CC_MCLK2_CLK_SRC] = &cam_cc_mclk2_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1651) [CAM_CC_MCLK3_CLK] = &cam_cc_mclk3_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1652) [CAM_CC_MCLK3_CLK_SRC] = &cam_cc_mclk3_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1653) [CAM_CC_PLL0] = &cam_cc_pll0.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1654) [CAM_CC_PLL0_OUT_EVEN] = &cam_cc_pll0_out_even.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1655) [CAM_CC_PLL1] = &cam_cc_pll1.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1656) [CAM_CC_PLL1_OUT_EVEN] = &cam_cc_pll1_out_even.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1657) [CAM_CC_PLL2] = &cam_cc_pll2.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1658) [CAM_CC_PLL2_OUT_EVEN] = &cam_cc_pll2_out_even.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1659) [CAM_CC_PLL3] = &cam_cc_pll3.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1660) [CAM_CC_PLL3_OUT_EVEN] = &cam_cc_pll3_out_even.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1661) [CAM_CC_SLOW_AHB_CLK_SRC] = &cam_cc_slow_ahb_clk_src.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1662) [CAM_CC_SOC_AHB_CLK] = &cam_cc_soc_ahb_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1663) [CAM_CC_SYS_TMR_CLK] = &cam_cc_sys_tmr_clk.clkr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1664) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1665)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1666) static struct gdsc *cam_cc_sdm845_gdscs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1667) [BPS_GDSC] = &bps_gdsc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1668) [IPE_0_GDSC] = &ipe_0_gdsc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1669) [IPE_1_GDSC] = &ipe_1_gdsc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1670) [IFE_0_GDSC] = &ife_0_gdsc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1671) [IFE_1_GDSC] = &ife_1_gdsc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1672) [TITAN_TOP_GDSC] = &titan_top_gdsc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1673) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1674)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1675) static const struct regmap_config cam_cc_sdm845_regmap_config = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1676) .reg_bits = 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1677) .reg_stride = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1678) .val_bits = 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1679) .max_register = 0xd004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1680) .fast_io = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1681) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1682)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1683) static const struct qcom_cc_desc cam_cc_sdm845_desc = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1684) .config = &cam_cc_sdm845_regmap_config,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1685) .clks = cam_cc_sdm845_clocks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1686) .num_clks = ARRAY_SIZE(cam_cc_sdm845_clocks),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1687) .gdscs = cam_cc_sdm845_gdscs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1688) .num_gdscs = ARRAY_SIZE(cam_cc_sdm845_gdscs),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1689) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1690)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1691) static const struct of_device_id cam_cc_sdm845_match_table[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1692) { .compatible = "qcom,sdm845-camcc" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1693) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1694) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1695) MODULE_DEVICE_TABLE(of, cam_cc_sdm845_match_table);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1696)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1697) static int cam_cc_sdm845_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1698) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1699) struct regmap *regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1700) struct alpha_pll_config cam_cc_pll_config = { };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1701)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1702) regmap = qcom_cc_map(pdev, &cam_cc_sdm845_desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1703) if (IS_ERR(regmap))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1704) return PTR_ERR(regmap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1705)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1706) cam_cc_pll_config.l = 0x1f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1707) cam_cc_pll_config.alpha = 0x4000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1708) clk_fabia_pll_configure(&cam_cc_pll0, regmap, &cam_cc_pll_config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1709)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1710) cam_cc_pll_config.l = 0x2a;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1711) cam_cc_pll_config.alpha = 0x1556;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1712) clk_fabia_pll_configure(&cam_cc_pll1, regmap, &cam_cc_pll_config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1713)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1714) cam_cc_pll_config.l = 0x32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1715) cam_cc_pll_config.alpha = 0x0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1716) clk_fabia_pll_configure(&cam_cc_pll2, regmap, &cam_cc_pll_config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1717)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1718) cam_cc_pll_config.l = 0x14;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1719) clk_fabia_pll_configure(&cam_cc_pll3, regmap, &cam_cc_pll_config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1720)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1721) return qcom_cc_really_probe(pdev, &cam_cc_sdm845_desc, regmap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1722) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1723)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1724) static struct platform_driver cam_cc_sdm845_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1725) .probe = cam_cc_sdm845_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1726) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1727) .name = "sdm845-camcc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1728) .of_match_table = cam_cc_sdm845_match_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1729) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1730) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1731)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1732) static int __init cam_cc_sdm845_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1733) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1734) return platform_driver_register(&cam_cc_sdm845_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1735) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1736) subsys_initcall(cam_cc_sdm845_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1737)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1738) static void __exit cam_cc_sdm845_exit(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1739) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1740) platform_driver_unregister(&cam_cc_sdm845_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1741) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1742) module_exit(cam_cc_sdm845_exit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1743)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1744) MODULE_DESCRIPTION("QTI CAM_CC SDM845 Driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1745) MODULE_LICENSE("GPL v2");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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