^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) // Copyright (c) 2018, The Linux Foundation. All rights reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) #include <linux/clk-provider.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) #include <linux/regmap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include "clk-alpha-pll.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) static const u8 ipq_pll_offsets[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) [PLL_OFF_L_VAL] = 0x08,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) [PLL_OFF_ALPHA_VAL] = 0x10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) [PLL_OFF_USER_CTL] = 0x18,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) [PLL_OFF_CONFIG_CTL] = 0x20,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) [PLL_OFF_CONFIG_CTL_U] = 0x24,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) [PLL_OFF_STATUS] = 0x28,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) [PLL_OFF_TEST_CTL] = 0x30,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) [PLL_OFF_TEST_CTL_U] = 0x34,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) static struct clk_alpha_pll ipq_pll = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) .offset = 0x0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) .regs = ipq_pll_offsets,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) .flags = SUPPORTS_DYNAMIC_UPDATE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) .clkr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) .enable_reg = 0x0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) .hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) .name = "a53pll",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) .parent_data = &(const struct clk_parent_data) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) .fw_name = "xo",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) .ops = &clk_alpha_pll_huayra_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) static const struct alpha_pll_config ipq_pll_config = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) .l = 0x37,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) .config_ctl_val = 0x04141200,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) .config_ctl_hi_val = 0x0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) .early_output_mask = BIT(3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) .main_output_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) static const struct regmap_config ipq_pll_regmap_config = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) .reg_bits = 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) .reg_stride = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) .val_bits = 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) .max_register = 0x40,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) .fast_io = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) static int apss_ipq_pll_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) struct device *dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) struct regmap *regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) base = devm_platform_ioremap_resource(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) if (IS_ERR(base))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) return PTR_ERR(base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) regmap = devm_regmap_init_mmio(dev, base, &ipq_pll_regmap_config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) if (IS_ERR(regmap))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) return PTR_ERR(regmap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) clk_alpha_pll_configure(&ipq_pll, regmap, &ipq_pll_config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) ret = devm_clk_register_regmap(dev, &ipq_pll.clkr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) return devm_of_clk_add_hw_provider(dev, of_clk_hw_simple_get,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) &ipq_pll.clkr.hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) static const struct of_device_id apss_ipq_pll_match_table[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) { .compatible = "qcom,ipq6018-a53pll" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) MODULE_DEVICE_TABLE(of, apss_ipq_pll_match_table);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) static struct platform_driver apss_ipq_pll_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) .probe = apss_ipq_pll_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) .name = "qcom-ipq-apss-pll",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) .of_match_table = apss_ipq_pll_match_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) module_platform_driver(apss_ipq_pll_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) MODULE_DESCRIPTION("Qualcomm technology Inc APSS ALPHA PLL Driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) MODULE_LICENSE("GPL v2");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
3 Commits
0 Branches
0 Tags