^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Qualcomm APCS clock controller driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (c) 2017, Linaro Limited
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Author: Georgi Djakov <georgi.djakov@linaro.org>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/clk-provider.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/regmap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include "clk-regmap.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include "clk-regmap-mux-div.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) static const u32 gpll0_a53cc_map[] = { 4, 5 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) static const struct clk_parent_data pdata[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) { .fw_name = "aux", .name = "gpll0_vote", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) { .fw_name = "pll", .name = "a53pll", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) * We use the notifier function for switching to a temporary safe configuration
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) * (mux and divider), while the A53 PLL is reconfigured.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) static int a53cc_notifier_cb(struct notifier_block *nb, unsigned long event,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) void *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) struct clk_regmap_mux_div *md = container_of(nb,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) struct clk_regmap_mux_div,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) clk_nb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) if (event == PRE_RATE_CHANGE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) /* set the mux and divider to safe frequency (400mhz) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) ret = mux_div_set_src_div(md, 4, 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) return notifier_from_errno(ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) static int qcom_apcs_msm8916_clk_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) struct device *dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) struct device *parent = dev->parent;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) struct clk_regmap_mux_div *a53cc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) struct regmap *regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) struct clk_init_data init = { };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) int ret = -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) regmap = dev_get_regmap(parent, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) if (!regmap) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) dev_err(dev, "failed to get regmap: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) a53cc = devm_kzalloc(dev, sizeof(*a53cc), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) if (!a53cc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) init.name = "a53mux";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) init.parent_data = pdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) init.num_parents = ARRAY_SIZE(pdata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) init.ops = &clk_regmap_mux_div_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) init.flags = CLK_SET_RATE_PARENT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) a53cc->clkr.hw.init = &init;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) a53cc->clkr.regmap = regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) a53cc->reg_offset = 0x50;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) a53cc->hid_width = 5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) a53cc->hid_shift = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) a53cc->src_width = 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) a53cc->src_shift = 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) a53cc->parent_map = gpll0_a53cc_map;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) a53cc->pclk = devm_clk_get(parent, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) if (IS_ERR(a53cc->pclk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) ret = PTR_ERR(a53cc->pclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) if (ret != -EPROBE_DEFER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) dev_err(dev, "failed to get clk: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) a53cc->clk_nb.notifier_call = a53cc_notifier_cb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) ret = clk_notifier_register(a53cc->pclk, &a53cc->clk_nb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) dev_err(dev, "failed to register clock notifier: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) ret = devm_clk_register_regmap(dev, &a53cc->clkr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) dev_err(dev, "failed to register regmap clock: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) ret = devm_of_clk_add_hw_provider(dev, of_clk_hw_simple_get,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) &a53cc->clkr.hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) dev_err(dev, "failed to add clock provider: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) platform_set_drvdata(pdev, a53cc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) err:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) clk_notifier_unregister(a53cc->pclk, &a53cc->clk_nb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) static int qcom_apcs_msm8916_clk_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) struct clk_regmap_mux_div *a53cc = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) clk_notifier_unregister(a53cc->pclk, &a53cc->clk_nb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) static struct platform_driver qcom_apcs_msm8916_clk_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) .probe = qcom_apcs_msm8916_clk_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) .remove = qcom_apcs_msm8916_clk_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) .name = "qcom-apcs-msm8916-clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) module_platform_driver(qcom_apcs_msm8916_clk_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) MODULE_AUTHOR("Georgi Djakov <georgi.djakov@linaro.org>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) MODULE_LICENSE("GPL v2");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) MODULE_DESCRIPTION("Qualcomm MSM8916 APCS clock driver");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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