^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Qualcomm A53 PLL driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (c) 2017, Linaro Limited
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Author: Georgi Djakov <georgi.djakov@linaro.org>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/clk-provider.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/regmap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include "clk-pll.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include "clk-regmap.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) static const struct pll_freq_tbl a53pll_freq[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) { 998400000, 52, 0x0, 0x1, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) { 1094400000, 57, 0x0, 0x1, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) { 1152000000, 62, 0x0, 0x1, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) { 1209600000, 63, 0x0, 0x1, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) { 1248000000, 65, 0x0, 0x1, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) { 1363200000, 71, 0x0, 0x1, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) { 1401600000, 73, 0x0, 0x1, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) static const struct regmap_config a53pll_regmap_config = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) .reg_bits = 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) .reg_stride = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) .val_bits = 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) .max_register = 0x40,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) .fast_io = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) static int qcom_a53pll_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) struct device *dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) struct regmap *regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) struct resource *res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) struct clk_pll *pll;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) struct clk_init_data init = { };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) pll = devm_kzalloc(dev, sizeof(*pll), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) if (!pll)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) base = devm_ioremap_resource(dev, res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) if (IS_ERR(base))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) return PTR_ERR(base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) regmap = devm_regmap_init_mmio(dev, base, &a53pll_regmap_config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) if (IS_ERR(regmap))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) return PTR_ERR(regmap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) pll->l_reg = 0x04;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) pll->m_reg = 0x08;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) pll->n_reg = 0x0c;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) pll->config_reg = 0x14;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) pll->mode_reg = 0x00;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) pll->status_reg = 0x1c;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) pll->status_bit = 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) pll->freq_tbl = a53pll_freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) init.name = "a53pll";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) init.parent_names = (const char *[]){ "xo" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) init.num_parents = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) init.ops = &clk_pll_sr2_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) init.flags = CLK_IS_CRITICAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) pll->clkr.hw.init = &init;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) ret = devm_clk_register_regmap(dev, &pll->clkr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) dev_err(dev, "failed to register regmap clock: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) ret = devm_of_clk_add_hw_provider(dev, of_clk_hw_simple_get,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) &pll->clkr.hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) dev_err(dev, "failed to add clock provider: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) static const struct of_device_id qcom_a53pll_match_table[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) { .compatible = "qcom,msm8916-a53pll" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) MODULE_DEVICE_TABLE(of, qcom_a53pll_match_table);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) static struct platform_driver qcom_a53pll_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) .probe = qcom_a53pll_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) .name = "qcom-a53pll",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) .of_match_table = qcom_a53pll_match_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) module_platform_driver(qcom_a53pll_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) MODULE_DESCRIPTION("Qualcomm A53 PLL Driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) MODULE_LICENSE("GPL v2");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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