^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Marvell PXA3xxx family clocks
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2014 Robert Jarzmik
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Heavily inspired from former arch/arm/mach-pxa/pxa3xx.c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * For non-devicetree platforms. Once pxa is fully converted to devicetree, this
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * should go away.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/clk-provider.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/clkdev.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <mach/smemc.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <mach/pxa3xx-regs.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <dt-bindings/clock/pxa-clock.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include "clk-pxa.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define KHz 1000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define MHz (1000 * 1000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) PXA_CORE_60Mhz = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) PXA_CORE_RUN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) PXA_CORE_TURBO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) PXA_BUS_60Mhz = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) PXA_BUS_HSS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) /* crystal frequency to HSIO bus frequency multiplier (HSS) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) static unsigned char hss_mult[4] = { 8, 12, 16, 24 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) /* crystal frequency to static memory controller multiplier (SMCFS) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) static unsigned int smcfs_mult[8] = { 6, 0, 8, 0, 0, 16, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) static unsigned int df_clkdiv[4] = { 1, 2, 4, 1 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) static const char * const get_freq_khz[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) "core", "ring_osc_60mhz", "run", "cpll", "system_bus"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) * Get the clock frequency as reflected by ACSR and the turbo flag.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) * We assume these values have been applied via a fcs.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) * If info is not 0 we also display the current settings.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) unsigned int pxa3xx_get_clk_frequency_khz(int info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) unsigned long clks[5];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) for (i = 0; i < 5; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) clk = clk_get(NULL, get_freq_khz[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) if (IS_ERR(clk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) clks[i] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) clks[i] = clk_get_rate(clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) clk_put(clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) if (info) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) pr_info("RO Mode clock: %ld.%02ldMHz\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) clks[1] / 1000000, (clks[0] % 1000000) / 10000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) pr_info("Run Mode clock: %ld.%02ldMHz\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) clks[2] / 1000000, (clks[1] % 1000000) / 10000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) pr_info("Turbo Mode clock: %ld.%02ldMHz\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) clks[3] / 1000000, (clks[2] % 1000000) / 10000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) pr_info("System bus clock: %ld.%02ldMHz\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) clks[4] / 1000000, (clks[4] % 1000000) / 10000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) return (unsigned int)clks[0] / KHz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) static unsigned long clk_pxa3xx_ac97_get_rate(struct clk_hw *hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) unsigned long parent_rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) unsigned long ac97_div, rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) ac97_div = AC97_DIV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) /* This may loose precision for some rates but won't for the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) * standard 24.576MHz.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) rate = parent_rate / 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) rate /= ((ac97_div >> 12) & 0x7fff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) rate *= (ac97_div & 0xfff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) return rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) PARENTS(clk_pxa3xx_ac97) = { "spll_624mhz" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) RATE_RO_OPS(clk_pxa3xx_ac97, "ac97");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) static unsigned long clk_pxa3xx_smemc_get_rate(struct clk_hw *hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) unsigned long parent_rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) unsigned long acsr = ACSR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) unsigned long memclkcfg = __raw_readl(MEMCLKCFG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) return (parent_rate / 48) * smcfs_mult[(acsr >> 23) & 0x7] /
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) df_clkdiv[(memclkcfg >> 16) & 0x3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) PARENTS(clk_pxa3xx_smemc) = { "spll_624mhz" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) RATE_RO_OPS(clk_pxa3xx_smemc, "smemc");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) static bool pxa3xx_is_ring_osc_forced(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) unsigned long acsr = ACSR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) return acsr & ACCR_D0CS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) PARENTS(pxa3xx_pbus) = { "ring_osc_60mhz", "spll_624mhz" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) PARENTS(pxa3xx_32Khz_bus) = { "osc_32_768khz", "osc_32_768khz" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) PARENTS(pxa3xx_13MHz_bus) = { "osc_13mhz", "osc_13mhz" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) PARENTS(pxa3xx_ac97_bus) = { "ring_osc_60mhz", "ac97" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) PARENTS(pxa3xx_sbus) = { "ring_osc_60mhz", "system_bus" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) PARENTS(pxa3xx_smemcbus) = { "ring_osc_60mhz", "smemc" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define CKEN_AB(bit) ((CKEN_ ## bit > 31) ? &CKENB : &CKENA)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define PXA3XX_CKEN(dev_id, con_id, parents, mult_lp, div_lp, mult_hp, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) div_hp, bit, is_lp, flags) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) PXA_CKEN(dev_id, con_id, bit, parents, mult_lp, div_lp, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) mult_hp, div_hp, is_lp, CKEN_AB(bit), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) (CKEN_ ## bit % 32), flags)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define PXA3XX_PBUS_CKEN(dev_id, con_id, bit, mult_lp, div_lp, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) mult_hp, div_hp, delay) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) PXA3XX_CKEN(dev_id, con_id, pxa3xx_pbus_parents, mult_lp, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) div_lp, mult_hp, div_hp, bit, pxa3xx_is_ring_osc_forced, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define PXA3XX_CKEN_1RATE(dev_id, con_id, bit, parents) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) PXA_CKEN_1RATE(dev_id, con_id, bit, parents, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) CKEN_AB(bit), (CKEN_ ## bit % 32), 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) static struct desc_clk_cken pxa3xx_clocks[] __initdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) PXA3XX_PBUS_CKEN("pxa2xx-uart.0", NULL, FFUART, 1, 4, 1, 42, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) PXA3XX_PBUS_CKEN("pxa2xx-uart.1", NULL, BTUART, 1, 4, 1, 42, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) PXA3XX_PBUS_CKEN("pxa2xx-uart.2", NULL, STUART, 1, 4, 1, 42, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) PXA3XX_PBUS_CKEN("pxa2xx-i2c.0", NULL, I2C, 2, 5, 1, 19, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) PXA3XX_PBUS_CKEN("pxa27x-udc", NULL, UDC, 1, 4, 1, 13, 5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) PXA3XX_PBUS_CKEN("pxa27x-ohci", NULL, USBH, 1, 4, 1, 13, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) PXA3XX_PBUS_CKEN("pxa3xx-u2d", NULL, USB2, 1, 4, 1, 13, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) PXA3XX_PBUS_CKEN("pxa27x-pwm.0", NULL, PWM0, 1, 6, 1, 48, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) PXA3XX_PBUS_CKEN("pxa27x-pwm.1", NULL, PWM1, 1, 6, 1, 48, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) PXA3XX_PBUS_CKEN("pxa2xx-mci.0", NULL, MMC1, 1, 4, 1, 24, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) PXA3XX_PBUS_CKEN("pxa2xx-mci.1", NULL, MMC2, 1, 4, 1, 24, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) PXA3XX_PBUS_CKEN("pxa2xx-mci.2", NULL, MMC3, 1, 4, 1, 24, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) PXA3XX_CKEN_1RATE("pxa27x-keypad", NULL, KEYPAD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) pxa3xx_32Khz_bus_parents),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) PXA3XX_CKEN_1RATE("pxa3xx-ssp.0", NULL, SSP1, pxa3xx_13MHz_bus_parents),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) PXA3XX_CKEN_1RATE("pxa3xx-ssp.1", NULL, SSP2, pxa3xx_13MHz_bus_parents),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) PXA3XX_CKEN_1RATE("pxa3xx-ssp.2", NULL, SSP3, pxa3xx_13MHz_bus_parents),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) PXA3XX_CKEN_1RATE("pxa3xx-ssp.3", NULL, SSP4, pxa3xx_13MHz_bus_parents),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) PXA3XX_CKEN(NULL, "AC97CLK", pxa3xx_ac97_bus_parents, 1, 4, 1, 1, AC97,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) pxa3xx_is_ring_osc_forced, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) PXA3XX_CKEN(NULL, "CAMCLK", pxa3xx_sbus_parents, 1, 2, 1, 1, CAMERA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) pxa3xx_is_ring_osc_forced, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) PXA3XX_CKEN("pxa2xx-fb", NULL, pxa3xx_sbus_parents, 1, 1, 1, 1, LCD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) pxa3xx_is_ring_osc_forced, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) PXA3XX_CKEN("pxa2xx-pcmcia", NULL, pxa3xx_smemcbus_parents, 1, 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 1, 1, SMC, pxa3xx_is_ring_osc_forced, CLK_IGNORE_UNUSED),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) static struct desc_clk_cken pxa300_310_clocks[] __initdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) PXA3XX_PBUS_CKEN("pxa3xx-gcu", NULL, PXA300_GCU, 1, 1, 1, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) PXA3XX_PBUS_CKEN("pxa3xx-nand", NULL, NAND, 1, 2, 1, 4, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) PXA3XX_CKEN_1RATE("pxa3xx-gpio", NULL, GPIO, pxa3xx_13MHz_bus_parents),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) static struct desc_clk_cken pxa320_clocks[] __initdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) PXA3XX_PBUS_CKEN("pxa3xx-nand", NULL, NAND, 1, 2, 1, 6, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) PXA3XX_PBUS_CKEN("pxa3xx-gcu", NULL, PXA320_GCU, 1, 1, 1, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) PXA3XX_CKEN_1RATE("pxa3xx-gpio", NULL, GPIO, pxa3xx_13MHz_bus_parents),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) static struct desc_clk_cken pxa93x_clocks[] __initdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) PXA3XX_PBUS_CKEN("pxa3xx-gcu", NULL, PXA300_GCU, 1, 1, 1, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) PXA3XX_PBUS_CKEN("pxa3xx-nand", NULL, NAND, 1, 2, 1, 4, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) PXA3XX_CKEN_1RATE("pxa93x-gpio", NULL, GPIO, pxa3xx_13MHz_bus_parents),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) static unsigned long clk_pxa3xx_system_bus_get_rate(struct clk_hw *hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) unsigned long parent_rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) unsigned long acsr = ACSR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) unsigned int hss = (acsr >> 14) & 0x3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) if (pxa3xx_is_ring_osc_forced())
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) return parent_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) return parent_rate / 48 * hss_mult[hss];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) static u8 clk_pxa3xx_system_bus_get_parent(struct clk_hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) if (pxa3xx_is_ring_osc_forced())
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) return PXA_BUS_60Mhz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) return PXA_BUS_HSS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) PARENTS(clk_pxa3xx_system_bus) = { "ring_osc_60mhz", "spll_624mhz" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) MUX_RO_RATE_RO_OPS(clk_pxa3xx_system_bus, "system_bus");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) static unsigned long clk_pxa3xx_core_get_rate(struct clk_hw *hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) unsigned long parent_rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) return parent_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) static u8 clk_pxa3xx_core_get_parent(struct clk_hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) unsigned long xclkcfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) unsigned int t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) if (pxa3xx_is_ring_osc_forced())
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) return PXA_CORE_60Mhz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) /* Read XCLKCFG register turbo bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) __asm__ __volatile__("mrc\tp14, 0, %0, c6, c0, 0" : "=r"(xclkcfg));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) t = xclkcfg & 0x1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) if (t)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) return PXA_CORE_TURBO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) return PXA_CORE_RUN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) PARENTS(clk_pxa3xx_core) = { "ring_osc_60mhz", "run", "cpll" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) MUX_RO_RATE_RO_OPS(clk_pxa3xx_core, "core");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) static unsigned long clk_pxa3xx_run_get_rate(struct clk_hw *hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) unsigned long parent_rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) unsigned long acsr = ACSR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) unsigned int xn = (acsr & ACCR_XN_MASK) >> 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) unsigned int t, xclkcfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) /* Read XCLKCFG register turbo bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) __asm__ __volatile__("mrc\tp14, 0, %0, c6, c0, 0" : "=r"(xclkcfg));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) t = xclkcfg & 0x1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) return t ? (parent_rate / xn) * 2 : parent_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) PARENTS(clk_pxa3xx_run) = { "cpll" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) RATE_RO_OPS(clk_pxa3xx_run, "run");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) static unsigned long clk_pxa3xx_cpll_get_rate(struct clk_hw *hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) unsigned long parent_rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) unsigned long acsr = ACSR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) unsigned int xn = (acsr & ACCR_XN_MASK) >> 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) unsigned int xl = acsr & ACCR_XL_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) unsigned int t, xclkcfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) /* Read XCLKCFG register turbo bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) __asm__ __volatile__("mrc\tp14, 0, %0, c6, c0, 0" : "=r"(xclkcfg));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) t = xclkcfg & 0x1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) pr_info("RJK: parent_rate=%lu, xl=%u, xn=%u\n", parent_rate, xl, xn);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) return t ? parent_rate * xl * xn : parent_rate * xl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) PARENTS(clk_pxa3xx_cpll) = { "osc_13mhz" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) RATE_RO_OPS(clk_pxa3xx_cpll, "cpll");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) static void __init pxa3xx_register_core(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) clk_register_clk_pxa3xx_cpll();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) clk_register_clk_pxa3xx_run();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) clkdev_pxa_register(CLK_CORE, "core", NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) clk_register_clk_pxa3xx_core());
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) static void __init pxa3xx_register_plls(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) clk_register_fixed_rate(NULL, "osc_13mhz", NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) CLK_GET_RATE_NOCACHE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) 13 * MHz);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) clkdev_pxa_register(CLK_OSC32k768, "osc_32_768khz", NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) clk_register_fixed_rate(NULL, "osc_32_768khz", NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) CLK_GET_RATE_NOCACHE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) 32768));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) clk_register_fixed_rate(NULL, "ring_osc_120mhz", NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) CLK_GET_RATE_NOCACHE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) 120 * MHz);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) clk_register_fixed_rate(NULL, "clk_dummy", NULL, 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) clk_register_fixed_factor(NULL, "spll_624mhz", "osc_13mhz", 0, 48, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) clk_register_fixed_factor(NULL, "ring_osc_60mhz", "ring_osc_120mhz",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) 0, 1, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) #define DUMMY_CLK(_con_id, _dev_id, _parent) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) { .con_id = _con_id, .dev_id = _dev_id, .parent = _parent }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) struct dummy_clk {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) const char *con_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) const char *dev_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) const char *parent;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) static struct dummy_clk dummy_clks[] __initdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) DUMMY_CLK(NULL, "pxa93x-gpio", "osc_13mhz"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) DUMMY_CLK(NULL, "sa1100-rtc", "osc_32_768khz"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) DUMMY_CLK("UARTCLK", "pxa2xx-ir", "STUART"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) DUMMY_CLK(NULL, "pxa3xx-pwri2c.1", "osc_13mhz"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) static void __init pxa3xx_dummy_clocks_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) struct dummy_clk *d;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) const char *name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) for (i = 0; i < ARRAY_SIZE(dummy_clks); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) d = &dummy_clks[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) name = d->dev_id ? d->dev_id : d->con_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) clk = clk_register_fixed_factor(NULL, name, d->parent, 0, 1, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) clk_register_clkdev(clk, d->con_id, d->dev_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) static void __init pxa3xx_base_clocks_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) pxa3xx_register_plls();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) pxa3xx_register_core();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) clk_register_clk_pxa3xx_system_bus();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) clk_register_clk_pxa3xx_ac97();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) clk_register_clk_pxa3xx_smemc();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) clk = clk_register_gate(NULL, "CLK_POUT",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) "osc_13mhz", 0, OSCC, 11, 0, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) clk_register_clkdev(clk, "CLK_POUT", NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) clkdev_pxa_register(CLK_OSTIMER, "OSTIMER0", NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) clk_register_fixed_factor(NULL, "os-timer0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) "osc_13mhz", 0, 1, 4));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) int __init pxa3xx_clocks_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) pxa3xx_base_clocks_init();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) pxa3xx_dummy_clocks_init();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) ret = clk_pxa_cken_init(pxa3xx_clocks, ARRAY_SIZE(pxa3xx_clocks));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) if (cpu_is_pxa320())
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) return clk_pxa_cken_init(pxa320_clocks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) ARRAY_SIZE(pxa320_clocks));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) if (cpu_is_pxa300() || cpu_is_pxa310())
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) return clk_pxa_cken_init(pxa300_310_clocks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) ARRAY_SIZE(pxa300_310_clocks));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) return clk_pxa_cken_init(pxa93x_clocks, ARRAY_SIZE(pxa93x_clocks));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) static void __init pxa3xx_dt_clocks_init(struct device_node *np)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) pxa3xx_clocks_init();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) clk_pxa_dt_common_init(np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) CLK_OF_DECLARE(pxa_clks, "marvell,pxa300-clocks", pxa3xx_dt_clocks_init);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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