^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Marvell PXA25x family clocks
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2014 Robert Jarzmik
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Heavily inspired from former arch/arm/mach-pxa/pxa25x.c.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * For non-devicetree platforms. Once pxa is fully converted to devicetree, this
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * should go away.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/clk-provider.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/clkdev.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <mach/pxa2xx-regs.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <mach/smemc.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <dt-bindings/clock/pxa-clock.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include "clk-pxa.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define KHz 1000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define MHz (1000 * 1000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) PXA_CORE_RUN = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) PXA_CORE_TURBO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define PXA25x_CLKCFG(T) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) (CLKCFG_FCS | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) ((T) ? CLKCFG_TURBO : 0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define PXA25x_CCCR(N2, M, L) (N2 << 7 | M << 5 | L)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define MDCNFG_DRAC2(mdcnfg) (((mdcnfg) >> 21) & 0x3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define MDCNFG_DRAC0(mdcnfg) (((mdcnfg) >> 5) & 0x3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) /* Define the refresh period in mSec for the SDRAM and the number of rows */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define SDRAM_TREF 64 /* standard 64ms SDRAM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) * Various clock factors driven by the CCCR register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) /* Crystal Frequency to Memory Frequency Multiplier (L) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) static unsigned char L_clk_mult[32] = { 0, 27, 32, 36, 40, 45, 0, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) /* Memory Frequency to Run Mode Frequency Multiplier (M) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) static unsigned char M_clk_mult[4] = { 0, 1, 2, 4 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) /* Run Mode Frequency to Turbo Mode Frequency Multiplier (N) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) /* Note: we store the value N * 2 here. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) static unsigned char N2_clk_mult[8] = { 0, 0, 2, 3, 4, 0, 6, 0 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) static const char * const get_freq_khz[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) "core", "run", "cpll", "memory"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) static int get_sdram_rows(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) static int sdram_rows;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) unsigned int drac2 = 0, drac0 = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) u32 mdcnfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) if (sdram_rows)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) return sdram_rows;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) mdcnfg = readl_relaxed(MDCNFG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) if (mdcnfg & (MDCNFG_DE2 | MDCNFG_DE3))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) drac2 = MDCNFG_DRAC2(mdcnfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) if (mdcnfg & (MDCNFG_DE0 | MDCNFG_DE1))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) drac0 = MDCNFG_DRAC0(mdcnfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) sdram_rows = 1 << (11 + max(drac0, drac2));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) return sdram_rows;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) static u32 mdrefr_dri(unsigned int freq_khz)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) u32 interval = freq_khz * SDRAM_TREF / get_sdram_rows();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) return interval / 32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) * Get the clock frequency as reflected by CCCR and the turbo flag.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) * We assume these values have been applied via a fcs.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) * If info is not 0 we also display the current settings.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) unsigned int pxa25x_get_clk_frequency_khz(int info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) unsigned long clks[5];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) for (i = 0; i < ARRAY_SIZE(get_freq_khz); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) clk = clk_get(NULL, get_freq_khz[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) if (IS_ERR(clk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) clks[i] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) clks[i] = clk_get_rate(clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) clk_put(clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) if (info) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) pr_info("Run Mode clock: %ld.%02ldMHz\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) clks[1] / 1000000, (clks[1] % 1000000) / 10000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) pr_info("Turbo Mode clock: %ld.%02ldMHz\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) clks[2] / 1000000, (clks[2] % 1000000) / 10000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) pr_info("Memory clock: %ld.%02ldMHz\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) clks[3] / 1000000, (clks[3] % 1000000) / 10000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) return (unsigned int)clks[0] / KHz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) static unsigned long clk_pxa25x_memory_get_rate(struct clk_hw *hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) unsigned long parent_rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) unsigned long cccr = readl(CCCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) unsigned int m = M_clk_mult[(cccr >> 5) & 0x03];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) return parent_rate / m;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) PARENTS(clk_pxa25x_memory) = { "run" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) RATE_RO_OPS(clk_pxa25x_memory, "memory");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) PARENTS(pxa25x_pbus95) = { "ppll_95_85mhz", "ppll_95_85mhz" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) PARENTS(pxa25x_pbus147) = { "ppll_147_46mhz", "ppll_147_46mhz" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) PARENTS(pxa25x_osc3) = { "osc_3_6864mhz", "osc_3_6864mhz" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define PXA25X_CKEN(dev_id, con_id, parents, mult, div, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) bit, is_lp, flags) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) PXA_CKEN(dev_id, con_id, bit, parents, mult, div, mult, div, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) is_lp, CKEN, CKEN_ ## bit, flags)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #define PXA25X_PBUS95_CKEN(dev_id, con_id, bit, mult_hp, div_hp, delay) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) PXA25X_CKEN(dev_id, con_id, pxa25x_pbus95_parents, mult_hp, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) div_hp, bit, NULL, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #define PXA25X_PBUS147_CKEN(dev_id, con_id, bit, mult_hp, div_hp, delay)\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) PXA25X_CKEN(dev_id, con_id, pxa25x_pbus147_parents, mult_hp, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) div_hp, bit, NULL, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #define PXA25X_OSC3_CKEN(dev_id, con_id, bit, mult_hp, div_hp, delay) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) PXA25X_CKEN(dev_id, con_id, pxa25x_osc3_parents, mult_hp, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) div_hp, bit, NULL, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #define PXA25X_CKEN_1RATE(dev_id, con_id, bit, parents, delay) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) PXA_CKEN_1RATE(dev_id, con_id, bit, parents, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) CKEN, CKEN_ ## bit, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) #define PXA25X_CKEN_1RATE_AO(dev_id, con_id, bit, parents, delay) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) PXA_CKEN_1RATE(dev_id, con_id, bit, parents, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) CKEN, CKEN_ ## bit, CLK_IGNORE_UNUSED)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) static struct desc_clk_cken pxa25x_clocks[] __initdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) PXA25X_PBUS95_CKEN("pxa2xx-mci.0", NULL, MMC, 1, 5, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) PXA25X_PBUS95_CKEN("pxa2xx-i2c.0", NULL, I2C, 1, 3, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) PXA25X_PBUS95_CKEN("pxa2xx-ir", "FICPCLK", FICP, 1, 2, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) PXA25X_PBUS95_CKEN("pxa25x-udc", NULL, USB, 1, 2, 5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) PXA25X_PBUS147_CKEN("pxa2xx-uart.0", NULL, FFUART, 1, 10, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) PXA25X_PBUS147_CKEN("pxa2xx-uart.1", NULL, BTUART, 1, 10, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) PXA25X_PBUS147_CKEN("pxa2xx-uart.2", NULL, STUART, 1, 10, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) PXA25X_PBUS147_CKEN("pxa2xx-uart.3", NULL, HWUART, 1, 10, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) PXA25X_PBUS147_CKEN("pxa2xx-i2s", NULL, I2S, 1, 10, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) PXA25X_PBUS147_CKEN(NULL, "AC97CLK", AC97, 1, 12, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) PXA25X_OSC3_CKEN("pxa25x-ssp.0", NULL, SSP, 1, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) PXA25X_OSC3_CKEN("pxa25x-nssp.1", NULL, NSSP, 1, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) PXA25X_OSC3_CKEN("pxa25x-nssp.2", NULL, ASSP, 1, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) PXA25X_OSC3_CKEN("pxa25x-pwm.0", NULL, PWM0, 1, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) PXA25X_OSC3_CKEN("pxa25x-pwm.1", NULL, PWM1, 1, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) PXA25X_CKEN_1RATE("pxa2xx-fb", NULL, LCD, clk_pxa25x_memory_parents, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) PXA25X_CKEN_1RATE_AO("pxa2xx-pcmcia", NULL, MEMC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) clk_pxa25x_memory_parents, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) * In this table, PXA25x_CCCR(N2, M, L) has the following meaning, where :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) * - freq_cpll = n * m * L * 3.6864 MHz
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) * - n = N2 / 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) * - m = 2^(M - 1), where 1 <= M <= 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) * - l = L_clk_mult[L], ie. { 0, 27, 32, 36, 40, 45, 0, }[L]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) static struct pxa2xx_freq pxa25x_freqs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) /* CPU MEMBUS CCCR DIV2 CCLKCFG */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) { 99532800, 99500, PXA25x_CCCR(2, 1, 1), 1, PXA25x_CLKCFG(1)},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) {199065600, 99500, PXA25x_CCCR(4, 1, 1), 0, PXA25x_CLKCFG(1)},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) {298598400, 99500, PXA25x_CCCR(3, 2, 1), 0, PXA25x_CLKCFG(1)},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) {398131200, 99500, PXA25x_CCCR(4, 2, 1), 0, PXA25x_CLKCFG(1)},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) static u8 clk_pxa25x_core_get_parent(struct clk_hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) unsigned long clkcfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) unsigned int t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) asm("mrc\tp14, 0, %0, c6, c0, 0" : "=r" (clkcfg));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) t = clkcfg & (1 << 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) if (t)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) return PXA_CORE_TURBO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) return PXA_CORE_RUN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) static int clk_pxa25x_core_set_parent(struct clk_hw *hw, u8 index)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) if (index > PXA_CORE_TURBO)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) pxa2xx_core_turbo_switch(index == PXA_CORE_TURBO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) static int clk_pxa25x_core_determine_rate(struct clk_hw *hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) struct clk_rate_request *req)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) return __clk_mux_determine_rate(hw, req);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) PARENTS(clk_pxa25x_core) = { "run", "cpll" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) MUX_OPS(clk_pxa25x_core, "core", CLK_SET_RATE_PARENT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) static unsigned long clk_pxa25x_run_get_rate(struct clk_hw *hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) unsigned long parent_rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) unsigned long cccr = readl(CCCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) unsigned int n2 = N2_clk_mult[(cccr >> 7) & 0x07];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) return (parent_rate / n2) * 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) PARENTS(clk_pxa25x_run) = { "cpll" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) RATE_RO_OPS(clk_pxa25x_run, "run");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) static unsigned long clk_pxa25x_cpll_get_rate(struct clk_hw *hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) unsigned long parent_rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) unsigned long clkcfg, cccr = readl(CCCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) unsigned int l, m, n2, t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) asm("mrc\tp14, 0, %0, c6, c0, 0" : "=r" (clkcfg));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) t = clkcfg & (1 << 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) l = L_clk_mult[(cccr >> 0) & 0x1f];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) m = M_clk_mult[(cccr >> 5) & 0x03];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) n2 = N2_clk_mult[(cccr >> 7) & 0x07];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) return m * l * n2 * parent_rate / 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) static int clk_pxa25x_cpll_determine_rate(struct clk_hw *hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) struct clk_rate_request *req)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) return pxa2xx_determine_rate(req, pxa25x_freqs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) ARRAY_SIZE(pxa25x_freqs));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) static int clk_pxa25x_cpll_set_rate(struct clk_hw *hw, unsigned long rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) unsigned long parent_rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) pr_debug("%s(rate=%lu parent_rate=%lu)\n", __func__, rate, parent_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) for (i = 0; i < ARRAY_SIZE(pxa25x_freqs); i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) if (pxa25x_freqs[i].cpll == rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) if (i >= ARRAY_SIZE(pxa25x_freqs))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) pxa2xx_cpll_change(&pxa25x_freqs[i], mdrefr_dri, MDREFR, CCCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) PARENTS(clk_pxa25x_cpll) = { "osc_3_6864mhz" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) RATE_OPS(clk_pxa25x_cpll, "cpll");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) static void __init pxa25x_register_core(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) clkdev_pxa_register(CLK_NONE, "cpll", NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) clk_register_clk_pxa25x_cpll());
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) clkdev_pxa_register(CLK_NONE, "run", NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) clk_register_clk_pxa25x_run());
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) clkdev_pxa_register(CLK_CORE, "core", NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) clk_register_clk_pxa25x_core());
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) static void __init pxa25x_register_plls(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) clk_register_fixed_rate(NULL, "osc_3_6864mhz", NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) CLK_GET_RATE_NOCACHE, 3686400);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) clkdev_pxa_register(CLK_OSC32k768, "osc_32_768khz", NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) clk_register_fixed_rate(NULL, "osc_32_768khz", NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) CLK_GET_RATE_NOCACHE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) 32768));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) clk_register_fixed_rate(NULL, "clk_dummy", NULL, 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) clk_register_fixed_factor(NULL, "ppll_95_85mhz", "osc_3_6864mhz",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) 0, 26, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) clk_register_fixed_factor(NULL, "ppll_147_46mhz", "osc_3_6864mhz",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) 0, 40, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) static void __init pxa25x_base_clocks_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) pxa25x_register_plls();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) pxa25x_register_core();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) clkdev_pxa_register(CLK_NONE, "system_bus", NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) clk_register_clk_pxa25x_memory());
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) #define DUMMY_CLK(_con_id, _dev_id, _parent) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) { .con_id = _con_id, .dev_id = _dev_id, .parent = _parent }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) struct dummy_clk {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) const char *con_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) const char *dev_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) const char *parent;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) static struct dummy_clk dummy_clks[] __initdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) DUMMY_CLK(NULL, "pxa25x-gpio", "osc_32_768khz"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) DUMMY_CLK(NULL, "pxa26x-gpio", "osc_32_768khz"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) DUMMY_CLK("GPIO11_CLK", NULL, "osc_3_6864mhz"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) DUMMY_CLK("GPIO12_CLK", NULL, "osc_32_768khz"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) DUMMY_CLK(NULL, "sa1100-rtc", "osc_32_768khz"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) DUMMY_CLK("OSTIMER0", NULL, "osc_3_6864mhz"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) DUMMY_CLK("UARTCLK", "pxa2xx-ir", "STUART"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) static void __init pxa25x_dummy_clocks_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) struct dummy_clk *d;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) const char *name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) * All pinctrl logic has been wiped out of the clock driver, especially
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) * for gpio11 and gpio12 outputs. Machine code should ensure proper pin
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) * control (ie. pxa2xx_mfp_config() invocation).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) for (i = 0; i < ARRAY_SIZE(dummy_clks); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) d = &dummy_clks[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) name = d->dev_id ? d->dev_id : d->con_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) clk = clk_register_fixed_factor(NULL, name, d->parent, 0, 1, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) clk_register_clkdev(clk, d->con_id, d->dev_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) int __init pxa25x_clocks_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) pxa25x_base_clocks_init();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) pxa25x_dummy_clocks_init();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) return clk_pxa_cken_init(pxa25x_clocks, ARRAY_SIZE(pxa25x_clocks));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) static void __init pxa25x_dt_clocks_init(struct device_node *np)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) pxa25x_clocks_init();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) clk_pxa_dt_common_init(np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) CLK_OF_DECLARE(pxa25x_clks, "marvell,pxa250-core-clocks",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) pxa25x_dt_clocks_init);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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