^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0-only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Marvell PXA family clocks
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2014 Robert Jarzmik
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Common clock code for PXA clocks ("CKEN" type clocks + DT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #ifndef _CLK_PXA_
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #define _CLK_PXA_
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #define CLKCFG_TURBO 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #define CLKCFG_FCS 0x2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #define CLKCFG_HALFTURBO 0x4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define CLKCFG_FASTBUS 0x8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define PARENTS(name) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) static const char *const name ## _parents[] __initconst
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define MUX_RO_RATE_RO_OPS(name, clk_name) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) static struct clk_hw name ## _mux_hw; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) static struct clk_hw name ## _rate_hw; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) static const struct clk_ops name ## _mux_ops = { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) .get_parent = name ## _get_parent, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) .set_parent = dummy_clk_set_parent, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) }; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) static const struct clk_ops name ## _rate_ops = { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) .recalc_rate = name ## _get_rate, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) }; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) static struct clk * __init clk_register_ ## name(void) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) return clk_register_composite(NULL, clk_name, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) name ## _parents, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) ARRAY_SIZE(name ## _parents), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) &name ## _mux_hw, &name ## _mux_ops, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) &name ## _rate_hw, &name ## _rate_ops, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) NULL, NULL, CLK_GET_RATE_NOCACHE); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define RATE_RO_OPS(name, clk_name) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) static struct clk_hw name ## _rate_hw; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) static const struct clk_ops name ## _rate_ops = { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) .recalc_rate = name ## _get_rate, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) }; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) static struct clk * __init clk_register_ ## name(void) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) return clk_register_composite(NULL, clk_name, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) name ## _parents, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) ARRAY_SIZE(name ## _parents), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) NULL, NULL, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) &name ## _rate_hw, &name ## _rate_ops, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) NULL, NULL, CLK_GET_RATE_NOCACHE); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define RATE_OPS(name, clk_name) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) static struct clk_hw name ## _rate_hw; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) static const struct clk_ops name ## _rate_ops = { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) .recalc_rate = name ## _get_rate, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) .set_rate = name ## _set_rate, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) .determine_rate = name ## _determine_rate, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) }; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) static struct clk * __init clk_register_ ## name(void) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) return clk_register_composite(NULL, clk_name, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) name ## _parents, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) ARRAY_SIZE(name ## _parents), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) NULL, NULL, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) &name ## _rate_hw, &name ## _rate_ops, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) NULL, NULL, CLK_GET_RATE_NOCACHE); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define MUX_OPS(name, clk_name, flags) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) static struct clk_hw name ## _mux_hw; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) static const struct clk_ops name ## _mux_ops = { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) .get_parent = name ## _get_parent, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) .set_parent = name ## _set_parent, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) .determine_rate = name ## _determine_rate, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) }; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) static struct clk * __init clk_register_ ## name(void) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) return clk_register_composite(NULL, clk_name, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) name ## _parents, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) ARRAY_SIZE(name ## _parents), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) &name ## _mux_hw, &name ## _mux_ops, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) NULL, NULL, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) NULL, NULL, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) CLK_GET_RATE_NOCACHE | flags); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) * CKEN clock type
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) * This clock takes it source from 2 possible parents :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) * - a low power parent
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) * - a normal parent
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) * +------------+ +-----------+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) * | Low Power | --- | x mult_lp |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) * | Clock | | / div_lp |\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) * +------------+ +-----------+ \+-----+ +-----------+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) * | Mux |---| CKEN gate |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) * +------------+ +-----------+ /+-----+ +-----------+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) * | High Power | | x mult_hp |/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) * | Clock | --- | / div_hp |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) * +------------+ +-----------+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) struct desc_clk_cken {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) struct clk_hw hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) int ckid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) const char *name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) const char *dev_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) const char *con_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) const char * const *parent_names;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) struct clk_fixed_factor lp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) struct clk_fixed_factor hp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) struct clk_gate gate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) bool (*is_in_low_power)(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) const unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define PXA_CKEN(_dev_id, _con_id, _name, parents, _mult_lp, _div_lp, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) _mult_hp, _div_hp, is_lp, _cken_reg, _cken_bit, flag) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) { .ckid = CLK_ ## _name, .name = #_name, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) .dev_id = _dev_id, .con_id = _con_id, .parent_names = parents,\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) .lp = { .mult = _mult_lp, .div = _div_lp }, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) .hp = { .mult = _mult_hp, .div = _div_hp }, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) .is_in_low_power = is_lp, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) .gate = { .reg = (void __iomem *)_cken_reg, .bit_idx = _cken_bit }, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) .flags = flag, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define PXA_CKEN_1RATE(dev_id, con_id, name, parents, cken_reg, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) cken_bit, flag) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) PXA_CKEN(dev_id, con_id, name, parents, 1, 1, 1, 1, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) NULL, cken_reg, cken_bit, flag)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) struct pxa2xx_freq {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) unsigned long cpll;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) unsigned int membus_khz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) unsigned int cccr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) unsigned int div2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) unsigned int clkcfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) static inline int dummy_clk_set_parent(struct clk_hw *hw, u8 index)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) extern void clkdev_pxa_register(int ckid, const char *con_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) const char *dev_id, struct clk *clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) extern int clk_pxa_cken_init(const struct desc_clk_cken *clks, int nb_clks);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) void clk_pxa_dt_common_init(struct device_node *np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) void pxa2xx_core_turbo_switch(bool on);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) void pxa2xx_cpll_change(struct pxa2xx_freq *freq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) u32 (*mdrefr_dri)(unsigned int), void __iomem *mdrefr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) void __iomem *cccr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) int pxa2xx_determine_rate(struct clk_rate_request *req,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) struct pxa2xx_freq *freqs, int nb_freqs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) #endif
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
3 Commits
0 Branches
0 Tags