Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * Pistachio SoC clock controllers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  * Copyright (C) 2014 Google, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8) #include <linux/clk-provider.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #include <dt-bindings/clock/pistachio-clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #include "clk.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) static struct pistachio_gate pistachio_gates[] __initdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) 	GATE(CLK_MIPS, "mips", "mips_div", 0x104, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) 	GATE(CLK_AUDIO_IN, "audio_in", "audio_clk_in_gate", 0x104, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) 	GATE(CLK_AUDIO, "audio", "audio_div", 0x104, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) 	GATE(CLK_I2S, "i2s", "i2s_div", 0x104, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) 	GATE(CLK_SPDIF, "spdif", "spdif_div", 0x104, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) 	GATE(CLK_AUDIO_DAC, "audio_dac", "audio_dac_div", 0x104, 5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) 	GATE(CLK_RPU_V, "rpu_v", "rpu_v_div", 0x104, 6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) 	GATE(CLK_RPU_L, "rpu_l", "rpu_l_div", 0x104, 7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) 	GATE(CLK_RPU_SLEEP, "rpu_sleep", "rpu_sleep_div", 0x104, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) 	GATE(CLK_WIFI_PLL_GATE, "wifi_pll_gate", "wifi_pll_mux", 0x104, 9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) 	GATE(CLK_RPU_CORE, "rpu_core", "rpu_core_div", 0x104, 10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) 	GATE(CLK_WIFI_ADC, "wifi_adc", "wifi_div8_mux", 0x104, 11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) 	GATE(CLK_WIFI_DAC, "wifi_dac", "wifi_div4_mux", 0x104, 12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) 	GATE(CLK_USB_PHY, "usb_phy", "usb_phy_div", 0x104, 13),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) 	GATE(CLK_ENET_IN, "enet_in", "enet_clk_in_gate", 0x104, 14),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) 	GATE(CLK_ENET, "enet", "enet_div", 0x104, 15),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) 	GATE(CLK_UART0, "uart0", "uart0_div", 0x104, 16),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) 	GATE(CLK_UART1, "uart1", "uart1_div", 0x104, 17),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) 	GATE(CLK_PERIPH_SYS, "periph_sys", "sys_internal_div", 0x104, 18),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) 	GATE(CLK_SPI0, "spi0", "spi0_div", 0x104, 19),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) 	GATE(CLK_SPI1, "spi1", "spi1_div", 0x104, 20),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) 	GATE(CLK_EVENT_TIMER, "event_timer", "event_timer_div", 0x104, 21),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) 	GATE(CLK_AUX_ADC_INTERNAL, "aux_adc_internal", "sys_internal_div",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) 	     0x104, 22),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) 	GATE(CLK_AUX_ADC, "aux_adc", "aux_adc_div", 0x104, 23),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) 	GATE(CLK_SD_HOST, "sd_host", "sd_host_div", 0x104, 24),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) 	GATE(CLK_BT, "bt", "bt_div", 0x104, 25),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) 	GATE(CLK_BT_DIV4, "bt_div4", "bt_div4_div", 0x104, 26),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) 	GATE(CLK_BT_DIV8, "bt_div8", "bt_div8_div", 0x104, 27),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) 	GATE(CLK_BT_1MHZ, "bt_1mhz", "bt_1mhz_div", 0x104, 28),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) static struct pistachio_fixed_factor pistachio_ffs[] __initdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) 	FIXED_FACTOR(CLK_WIFI_DIV4, "wifi_div4", "wifi_pll", 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) 	FIXED_FACTOR(CLK_WIFI_DIV8, "wifi_div8", "wifi_pll", 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) static struct pistachio_div pistachio_divs[] __initdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) 	DIV(CLK_MIPS_INTERNAL_DIV, "mips_internal_div", "mips_pll_mux",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) 	    0x204, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 	DIV(CLK_MIPS_DIV, "mips_div", "mips_internal_div", 0x208, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) 	DIV_F(CLK_AUDIO_DIV, "audio_div", "audio_mux",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 		0x20c, 8, CLK_DIVIDER_ROUND_CLOSEST),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 	DIV_F(CLK_I2S_DIV, "i2s_div", "audio_pll_mux",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 		0x210, 8, CLK_DIVIDER_ROUND_CLOSEST),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 	DIV_F(CLK_SPDIF_DIV, "spdif_div", "audio_pll_mux",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 		0x214, 8, CLK_DIVIDER_ROUND_CLOSEST),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 	DIV_F(CLK_AUDIO_DAC_DIV, "audio_dac_div", "audio_pll_mux",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) 		0x218, 8, CLK_DIVIDER_ROUND_CLOSEST),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 	DIV(CLK_RPU_V_DIV, "rpu_v_div", "rpu_v_pll_mux", 0x21c, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 	DIV(CLK_RPU_L_DIV, "rpu_l_div", "rpu_l_mux", 0x220, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 	DIV(CLK_RPU_SLEEP_DIV, "rpu_sleep_div", "xtal", 0x224, 10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 	DIV(CLK_RPU_CORE_DIV, "rpu_core_div", "rpu_core_mux", 0x228, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 	DIV(CLK_USB_PHY_DIV, "usb_phy_div", "sys_internal_div", 0x22c, 6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 	DIV(CLK_ENET_DIV, "enet_div", "enet_mux", 0x230, 6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 	DIV_F(CLK_UART0_INTERNAL_DIV, "uart0_internal_div", "sys_pll_mux",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 	      0x234, 3, CLK_DIVIDER_ROUND_CLOSEST),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 	DIV_F(CLK_UART0_DIV, "uart0_div", "uart0_internal_div", 0x238, 10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 	      CLK_DIVIDER_ROUND_CLOSEST),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 	DIV_F(CLK_UART1_INTERNAL_DIV, "uart1_internal_div", "sys_pll_mux",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 	      0x23c, 3, CLK_DIVIDER_ROUND_CLOSEST),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 	DIV_F(CLK_UART1_DIV, "uart1_div", "uart1_internal_div", 0x240, 10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 	      CLK_DIVIDER_ROUND_CLOSEST),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 	DIV(CLK_SYS_INTERNAL_DIV, "sys_internal_div", "sys_pll_mux", 0x244, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 	DIV(CLK_SPI0_INTERNAL_DIV, "spi0_internal_div", "sys_pll_mux",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 	    0x248, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 	DIV(CLK_SPI0_DIV, "spi0_div", "spi0_internal_div", 0x24c, 7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 	DIV(CLK_SPI1_INTERNAL_DIV, "spi1_internal_div", "sys_pll_mux",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 	    0x250, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 	DIV(CLK_SPI1_DIV, "spi1_div", "spi1_internal_div", 0x254, 7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 	DIV(CLK_EVENT_TIMER_INTERNAL_DIV, "event_timer_internal_div",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 	    "event_timer_mux", 0x258, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 	DIV(CLK_EVENT_TIMER_DIV, "event_timer_div", "event_timer_internal_div",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 	    0x25c, 12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 	DIV(CLK_AUX_ADC_INTERNAL_DIV, "aux_adc_internal_div",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 	    "aux_adc_internal", 0x260, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 	DIV(CLK_AUX_ADC_DIV, "aux_adc_div", "aux_adc_internal_div", 0x264, 10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 	DIV(CLK_SD_HOST_DIV, "sd_host_div", "sd_host_mux", 0x268, 6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 	DIV(CLK_BT_DIV, "bt_div", "bt_pll_mux", 0x26c, 6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 	DIV(CLK_BT_DIV4_DIV, "bt_div4_div", "bt_pll_mux", 0x270, 6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 	DIV(CLK_BT_DIV8_DIV, "bt_div8_div", "bt_pll_mux", 0x274, 6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 	DIV(CLK_BT_1MHZ_INTERNAL_DIV, "bt_1mhz_internal_div", "bt_pll_mux",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 	    0x278, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 	DIV(CLK_BT_1MHZ_DIV, "bt_1mhz_div", "bt_1mhz_internal_div", 0x27c, 10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) PNAME(mux_xtal_audio_refclk) = { "xtal", "audio_clk_in_gate" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) PNAME(mux_xtal_mips) = { "xtal", "mips_pll" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) PNAME(mux_xtal_audio) = { "xtal", "audio_pll", "audio_in" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) PNAME(mux_audio_debug) = { "audio_pll_mux", "debug_mux" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) PNAME(mux_xtal_rpu_v) = { "xtal", "rpu_v_pll" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) PNAME(mux_xtal_rpu_l) = { "xtal", "rpu_l_pll" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) PNAME(mux_rpu_l_mips) = { "rpu_l_pll_mux", "mips_pll_mux" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) PNAME(mux_xtal_wifi) = { "xtal", "wifi_pll" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) PNAME(mux_xtal_wifi_div4) = { "xtal", "wifi_div4" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) PNAME(mux_xtal_wifi_div8) = { "xtal", "wifi_div8" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) PNAME(mux_wifi_div4_rpu_l) = { "wifi_pll_gate", "wifi_div4_mux",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 			       "rpu_l_pll_mux" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) PNAME(mux_xtal_sys) = { "xtal", "sys_pll" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) PNAME(mux_sys_enet) = { "sys_internal_div", "enet_in" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) PNAME(mux_audio_sys) = { "audio_pll_mux", "sys_internal_div" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) PNAME(mux_sys_bt) = { "sys_internal_div", "bt_pll_mux" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) PNAME(mux_xtal_bt) = { "xtal", "bt_pll" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) static struct pistachio_mux pistachio_muxes[] __initdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 	MUX(CLK_AUDIO_REF_MUX, "audio_refclk_mux", mux_xtal_audio_refclk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 	    0x200, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 	MUX(CLK_MIPS_PLL_MUX, "mips_pll_mux", mux_xtal_mips, 0x200, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 	MUX(CLK_AUDIO_PLL_MUX, "audio_pll_mux", mux_xtal_audio, 0x200, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 	MUX(CLK_AUDIO_MUX, "audio_mux", mux_audio_debug, 0x200, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 	MUX(CLK_RPU_V_PLL_MUX, "rpu_v_pll_mux", mux_xtal_rpu_v, 0x200, 5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 	MUX(CLK_RPU_L_PLL_MUX, "rpu_l_pll_mux", mux_xtal_rpu_l, 0x200, 6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 	MUX(CLK_RPU_L_MUX, "rpu_l_mux", mux_rpu_l_mips, 0x200, 7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 	MUX(CLK_WIFI_PLL_MUX, "wifi_pll_mux", mux_xtal_wifi, 0x200, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 	MUX(CLK_WIFI_DIV4_MUX, "wifi_div4_mux", mux_xtal_wifi_div4, 0x200, 9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 	MUX(CLK_WIFI_DIV8_MUX, "wifi_div8_mux", mux_xtal_wifi_div8, 0x200, 10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 	MUX(CLK_RPU_CORE_MUX, "rpu_core_mux", mux_wifi_div4_rpu_l, 0x200, 11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 	MUX(CLK_SYS_PLL_MUX, "sys_pll_mux", mux_xtal_sys, 0x200, 13),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 	MUX(CLK_ENET_MUX, "enet_mux", mux_sys_enet, 0x200, 14),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 	MUX(CLK_EVENT_TIMER_MUX, "event_timer_mux", mux_audio_sys, 0x200, 15),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 	MUX(CLK_SD_HOST_MUX, "sd_host_mux", mux_sys_bt, 0x200, 16),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 	MUX(CLK_BT_PLL_MUX, "bt_pll_mux", mux_xtal_bt, 0x200, 17),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) static struct pistachio_pll pistachio_plls[] __initdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 	PLL_FIXED(CLK_MIPS_PLL, "mips_pll", "xtal", PLL_GF40LP_LAINT, 0x0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 	PLL_FIXED(CLK_AUDIO_PLL, "audio_pll", "audio_refclk_mux",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 		  PLL_GF40LP_FRAC, 0xc),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 	PLL_FIXED(CLK_RPU_V_PLL, "rpu_v_pll", "xtal", PLL_GF40LP_LAINT, 0x20),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 	PLL_FIXED(CLK_RPU_L_PLL, "rpu_l_pll", "xtal", PLL_GF40LP_LAINT, 0x2c),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 	PLL_FIXED(CLK_SYS_PLL, "sys_pll", "xtal", PLL_GF40LP_FRAC, 0x38),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 	PLL_FIXED(CLK_WIFI_PLL, "wifi_pll", "xtal", PLL_GF40LP_FRAC, 0x4c),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 	PLL_FIXED(CLK_BT_PLL, "bt_pll", "xtal", PLL_GF40LP_LAINT, 0x60),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) PNAME(mux_debug) = { "mips_pll_mux", "rpu_v_pll_mux",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 		     "rpu_l_pll_mux", "sys_pll_mux",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 		     "wifi_pll_mux", "bt_pll_mux" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) static u32 mux_debug_idx[] = { 0x0, 0x1, 0x2, 0x4, 0x8, 0x10 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) static unsigned int pistachio_critical_clks_core[] __initdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 	CLK_MIPS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) static unsigned int pistachio_critical_clks_sys[] __initdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 	PERIPH_CLK_SYS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 	PERIPH_CLK_SYS_BUS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 	PERIPH_CLK_DDR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 	PERIPH_CLK_ROM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) static void __init pistachio_clk_init(struct device_node *np)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 	struct pistachio_clk_provider *p;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 	struct clk *debug_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 	p = pistachio_clk_alloc_provider(np, CLK_NR_CLKS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 	if (!p)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 		return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 	pistachio_clk_register_pll(p, pistachio_plls,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 				   ARRAY_SIZE(pistachio_plls));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 	pistachio_clk_register_mux(p, pistachio_muxes,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 				   ARRAY_SIZE(pistachio_muxes));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 	pistachio_clk_register_div(p, pistachio_divs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 				   ARRAY_SIZE(pistachio_divs));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 	pistachio_clk_register_fixed_factor(p, pistachio_ffs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 					    ARRAY_SIZE(pistachio_ffs));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 	pistachio_clk_register_gate(p, pistachio_gates,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 				    ARRAY_SIZE(pistachio_gates));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 	debug_clk = clk_register_mux_table(NULL, "debug_mux", mux_debug,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 					   ARRAY_SIZE(mux_debug),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 					   CLK_SET_RATE_NO_REPARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 					   p->base + 0x200, 18, 0x1f, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 					   mux_debug_idx, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 	p->clk_data.clks[CLK_DEBUG_MUX] = debug_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 	pistachio_clk_register_provider(p);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 	pistachio_clk_force_enable(p, pistachio_critical_clks_core,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 				   ARRAY_SIZE(pistachio_critical_clks_core));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) CLK_OF_DECLARE(pistachio_clk, "img,pistachio-clk", pistachio_clk_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) static struct pistachio_gate pistachio_periph_gates[] __initdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 	GATE(PERIPH_CLK_SYS, "sys", "periph_sys", 0x100, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 	GATE(PERIPH_CLK_SYS_BUS, "bus_sys", "periph_sys", 0x100, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 	GATE(PERIPH_CLK_DDR, "ddr", "periph_sys", 0x100, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 	GATE(PERIPH_CLK_ROM, "rom", "rom_div", 0x100, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 	GATE(PERIPH_CLK_COUNTER_FAST, "counter_fast", "counter_fast_div",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 	     0x100, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 	GATE(PERIPH_CLK_COUNTER_SLOW, "counter_slow", "counter_slow_div",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 	     0x100, 5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 	GATE(PERIPH_CLK_IR, "ir", "ir_div", 0x100, 6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 	GATE(PERIPH_CLK_WD, "wd", "wd_div", 0x100, 7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 	GATE(PERIPH_CLK_PDM, "pdm", "pdm_div", 0x100, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 	GATE(PERIPH_CLK_PWM, "pwm", "pwm_div", 0x100, 9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 	GATE(PERIPH_CLK_I2C0, "i2c0", "i2c0_div", 0x100, 10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 	GATE(PERIPH_CLK_I2C1, "i2c1", "i2c1_div", 0x100, 11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 	GATE(PERIPH_CLK_I2C2, "i2c2", "i2c2_div", 0x100, 12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 	GATE(PERIPH_CLK_I2C3, "i2c3", "i2c3_div", 0x100, 13),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) static struct pistachio_div pistachio_periph_divs[] __initdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 	DIV(PERIPH_CLK_ROM_DIV, "rom_div", "periph_sys", 0x10c, 7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 	DIV(PERIPH_CLK_COUNTER_FAST_DIV, "counter_fast_div", "periph_sys",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 	    0x110, 7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 	DIV(PERIPH_CLK_COUNTER_SLOW_PRE_DIV, "counter_slow_pre_div",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 	    "periph_sys", 0x114, 7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 	DIV(PERIPH_CLK_COUNTER_SLOW_DIV, "counter_slow_div",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 	    "counter_slow_pre_div", 0x118, 7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 	DIV_F(PERIPH_CLK_IR_PRE_DIV, "ir_pre_div", "periph_sys", 0x11c, 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 	      CLK_DIVIDER_ROUND_CLOSEST),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 	DIV_F(PERIPH_CLK_IR_DIV, "ir_div", "ir_pre_div", 0x120, 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 	      CLK_DIVIDER_ROUND_CLOSEST),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 	DIV_F(PERIPH_CLK_WD_PRE_DIV, "wd_pre_div", "periph_sys", 0x124, 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 	      CLK_DIVIDER_ROUND_CLOSEST),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 	DIV_F(PERIPH_CLK_WD_DIV, "wd_div", "wd_pre_div", 0x128, 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 	      CLK_DIVIDER_ROUND_CLOSEST),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 	DIV(PERIPH_CLK_PDM_PRE_DIV, "pdm_pre_div", "periph_sys", 0x12c, 7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 	DIV(PERIPH_CLK_PDM_DIV, "pdm_div", "pdm_pre_div", 0x130, 7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 	DIV(PERIPH_CLK_PWM_PRE_DIV, "pwm_pre_div", "periph_sys", 0x134, 7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 	DIV(PERIPH_CLK_PWM_DIV, "pwm_div", "pwm_pre_div", 0x138, 7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 	DIV(PERIPH_CLK_I2C0_PRE_DIV, "i2c0_pre_div", "periph_sys", 0x13c, 7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 	DIV(PERIPH_CLK_I2C0_DIV, "i2c0_div", "i2c0_pre_div", 0x140, 7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 	DIV(PERIPH_CLK_I2C1_PRE_DIV, "i2c1_pre_div", "periph_sys", 0x144, 7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 	DIV(PERIPH_CLK_I2C1_DIV, "i2c1_div", "i2c1_pre_div", 0x148, 7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 	DIV(PERIPH_CLK_I2C2_PRE_DIV, "i2c2_pre_div", "periph_sys", 0x14c, 7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 	DIV(PERIPH_CLK_I2C2_DIV, "i2c2_div", "i2c2_pre_div", 0x150, 7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 	DIV(PERIPH_CLK_I2C3_PRE_DIV, "i2c3_pre_div", "periph_sys", 0x154, 7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 	DIV(PERIPH_CLK_I2C3_DIV, "i2c3_div", "i2c3_pre_div", 0x158, 7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) static void __init pistachio_clk_periph_init(struct device_node *np)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) 	struct pistachio_clk_provider *p;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) 	p = pistachio_clk_alloc_provider(np, PERIPH_CLK_NR_CLKS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) 	if (!p)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) 		return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) 	pistachio_clk_register_div(p, pistachio_periph_divs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) 				   ARRAY_SIZE(pistachio_periph_divs));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) 	pistachio_clk_register_gate(p, pistachio_periph_gates,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) 				    ARRAY_SIZE(pistachio_periph_gates));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) 	pistachio_clk_register_provider(p);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) 	pistachio_clk_force_enable(p, pistachio_critical_clks_sys,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) 				   ARRAY_SIZE(pistachio_critical_clks_sys));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) CLK_OF_DECLARE(pistachio_clk_periph, "img,pistachio-clk-periph",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) 	       pistachio_clk_periph_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) static struct pistachio_gate pistachio_sys_gates[] __initdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) 	GATE(SYS_CLK_I2C0, "i2c0_sys", "sys", 0x8, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) 	GATE(SYS_CLK_I2C1, "i2c1_sys", "sys", 0x8, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) 	GATE(SYS_CLK_I2C2, "i2c2_sys", "sys", 0x8, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) 	GATE(SYS_CLK_I2C3, "i2c3_sys", "sys", 0x8, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) 	GATE(SYS_CLK_I2S_IN, "i2s_in_sys", "sys", 0x8, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) 	GATE(SYS_CLK_PAUD_OUT, "paud_out_sys", "sys", 0x8, 5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) 	GATE(SYS_CLK_SPDIF_OUT, "spdif_out_sys", "sys", 0x8, 6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) 	GATE(SYS_CLK_SPI0_MASTER, "spi0_master_sys", "sys", 0x8, 7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) 	GATE(SYS_CLK_SPI0_SLAVE, "spi0_slave_sys", "sys", 0x8, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) 	GATE(SYS_CLK_PWM, "pwm_sys", "sys", 0x8, 9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) 	GATE(SYS_CLK_UART0, "uart0_sys", "sys", 0x8, 10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) 	GATE(SYS_CLK_UART1, "uart1_sys", "sys", 0x8, 11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) 	GATE(SYS_CLK_SPI1, "spi1_sys", "sys", 0x8, 12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) 	GATE(SYS_CLK_MDC, "mdc_sys", "sys", 0x8, 13),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) 	GATE(SYS_CLK_SD_HOST, "sd_host_sys", "sys", 0x8, 14),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) 	GATE(SYS_CLK_ENET, "enet_sys", "sys", 0x8, 15),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) 	GATE(SYS_CLK_IR, "ir_sys", "sys", 0x8, 16),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) 	GATE(SYS_CLK_WD, "wd_sys", "sys", 0x8, 17),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) 	GATE(SYS_CLK_TIMER, "timer_sys", "sys", 0x8, 18),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) 	GATE(SYS_CLK_I2S_OUT, "i2s_out_sys", "sys", 0x8, 24),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) 	GATE(SYS_CLK_SPDIF_IN, "spdif_in_sys", "sys", 0x8, 25),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) 	GATE(SYS_CLK_EVENT_TIMER, "event_timer_sys", "sys", 0x8, 26),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) 	GATE(SYS_CLK_HASH, "hash_sys", "sys", 0x8, 27),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) static void __init pistachio_cr_periph_init(struct device_node *np)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) 	struct pistachio_clk_provider *p;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) 	p = pistachio_clk_alloc_provider(np, SYS_CLK_NR_CLKS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) 	if (!p)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) 		return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) 	pistachio_clk_register_gate(p, pistachio_sys_gates,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) 				    ARRAY_SIZE(pistachio_sys_gates));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) 	pistachio_clk_register_provider(p);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) CLK_OF_DECLARE(pistachio_cr_periph, "img,pistachio-cr-periph",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) 	       pistachio_cr_periph_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) static struct pistachio_gate pistachio_ext_gates[] __initdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) 	GATE(EXT_CLK_ENET_IN, "enet_clk_in_gate", "enet_clk_in", 0x58, 5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) 	GATE(EXT_CLK_AUDIO_IN, "audio_clk_in_gate", "audio_clk_in", 0x58, 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) static void __init pistachio_cr_top_init(struct device_node *np)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) 	struct pistachio_clk_provider *p;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) 	p = pistachio_clk_alloc_provider(np, EXT_CLK_NR_CLKS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) 	if (!p)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) 		return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) 	pistachio_clk_register_gate(p, pistachio_ext_gates,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) 				    ARRAY_SIZE(pistachio_ext_gates));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) 	pistachio_clk_register_provider(p);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) CLK_OF_DECLARE(pistachio_cr_top, "img,pistachio-cr-top",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) 	       pistachio_cr_top_init);