^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright 2015 Vladimir Zapolskiy <vz@mleia.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include <linux/clk-provider.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/of_address.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/regmap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <dt-bindings/clock/lpc32xx-clock.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #undef pr_fmt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define pr_fmt(fmt) "%s: " fmt, __func__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) /* Common bitfield definitions for x397 PLL (lock), USB PLL and HCLK PLL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define PLL_CTRL_ENABLE BIT(16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define PLL_CTRL_BYPASS BIT(15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define PLL_CTRL_DIRECT BIT(14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define PLL_CTRL_FEEDBACK BIT(13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define PLL_CTRL_POSTDIV (BIT(12)|BIT(11))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define PLL_CTRL_PREDIV (BIT(10)|BIT(9))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define PLL_CTRL_FEEDDIV (0xFF << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define PLL_CTRL_LOCK BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) /* Clock registers on System Control Block */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define LPC32XX_CLKPWR_DEBUG_CTRL 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define LPC32XX_CLKPWR_USB_DIV 0x1C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define LPC32XX_CLKPWR_HCLKDIV_CTRL 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define LPC32XX_CLKPWR_PWR_CTRL 0x44
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define LPC32XX_CLKPWR_PLL397_CTRL 0x48
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define LPC32XX_CLKPWR_OSC_CTRL 0x4C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define LPC32XX_CLKPWR_SYSCLK_CTRL 0x50
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define LPC32XX_CLKPWR_LCDCLK_CTRL 0x54
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define LPC32XX_CLKPWR_HCLKPLL_CTRL 0x58
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define LPC32XX_CLKPWR_ADCCLK_CTRL1 0x60
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define LPC32XX_CLKPWR_USB_CTRL 0x64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define LPC32XX_CLKPWR_SSP_CTRL 0x78
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define LPC32XX_CLKPWR_I2S_CTRL 0x7C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define LPC32XX_CLKPWR_MS_CTRL 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define LPC32XX_CLKPWR_MACCLK_CTRL 0x90
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define LPC32XX_CLKPWR_TEST_CLK_CTRL 0xA4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define LPC32XX_CLKPWR_I2CCLK_CTRL 0xAC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define LPC32XX_CLKPWR_KEYCLK_CTRL 0xB0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define LPC32XX_CLKPWR_ADCCLK_CTRL 0xB4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define LPC32XX_CLKPWR_PWMCLK_CTRL 0xB8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define LPC32XX_CLKPWR_TIMCLK_CTRL 0xBC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define LPC32XX_CLKPWR_TIMCLK_CTRL1 0xC0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define LPC32XX_CLKPWR_SPI_CTRL 0xC4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define LPC32XX_CLKPWR_FLASHCLK_CTRL 0xC8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define LPC32XX_CLKPWR_UART3_CLK_CTRL 0xD0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define LPC32XX_CLKPWR_UART4_CLK_CTRL 0xD4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define LPC32XX_CLKPWR_UART5_CLK_CTRL 0xD8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define LPC32XX_CLKPWR_UART6_CLK_CTRL 0xDC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define LPC32XX_CLKPWR_IRDA_CLK_CTRL 0xE0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define LPC32XX_CLKPWR_UART_CLK_CTRL 0xE4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define LPC32XX_CLKPWR_DMA_CLK_CTRL 0xE8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) /* Clock registers on USB controller */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define LPC32XX_USB_CLK_CTRL 0xF4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define LPC32XX_USB_CLK_STS 0xF8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) static struct regmap_config lpc32xx_scb_regmap_config = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) .name = "scb",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) .reg_bits = 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) .val_bits = 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) .reg_stride = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) .val_format_endian = REGMAP_ENDIAN_LITTLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) .max_register = 0x114,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) .fast_io = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) static struct regmap *clk_regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) static void __iomem *usb_clk_vbase;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) LPC32XX_USB_CLK_OTG = LPC32XX_USB_CLK_HOST + 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) LPC32XX_USB_CLK_AHB,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) LPC32XX_USB_CLK_MAX = LPC32XX_USB_CLK_AHB + 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) /* Start from the last defined clock in dt bindings */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) LPC32XX_CLK_ADC_DIV = LPC32XX_CLK_PERIPH + 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) LPC32XX_CLK_ADC_RTC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) LPC32XX_CLK_TEST1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) LPC32XX_CLK_TEST2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) /* System clocks, PLL 397x and HCLK PLL clocks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) LPC32XX_CLK_OSC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) LPC32XX_CLK_SYS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) LPC32XX_CLK_PLL397X,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) LPC32XX_CLK_HCLK_DIV_PERIPH,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) LPC32XX_CLK_HCLK_DIV,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) LPC32XX_CLK_HCLK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) LPC32XX_CLK_ARM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) LPC32XX_CLK_ARM_VFP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) /* USB clocks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) LPC32XX_CLK_USB_PLL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) LPC32XX_CLK_USB_DIV,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) LPC32XX_CLK_USB,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) /* Only one control PWR_CTRL[10] for both muxes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) LPC32XX_CLK_PERIPH_HCLK_MUX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) LPC32XX_CLK_PERIPH_ARM_MUX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) /* Only one control PWR_CTRL[2] for all three muxes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) LPC32XX_CLK_SYSCLK_PERIPH_MUX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) LPC32XX_CLK_SYSCLK_HCLK_MUX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) LPC32XX_CLK_SYSCLK_ARM_MUX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) /* Two clock sources external to the driver */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) LPC32XX_CLK_XTAL_32K,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) LPC32XX_CLK_XTAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) /* Renumbered USB clocks, may have a parent from SCB table */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) LPC32XX_CLK_USB_OFFSET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) LPC32XX_CLK_USB_I2C = LPC32XX_USB_CLK_I2C + LPC32XX_CLK_USB_OFFSET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) LPC32XX_CLK_USB_DEV = LPC32XX_USB_CLK_DEVICE + LPC32XX_CLK_USB_OFFSET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) LPC32XX_CLK_USB_HOST = LPC32XX_USB_CLK_HOST + LPC32XX_CLK_USB_OFFSET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) LPC32XX_CLK_USB_OTG = LPC32XX_USB_CLK_OTG + LPC32XX_CLK_USB_OFFSET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) LPC32XX_CLK_USB_AHB = LPC32XX_USB_CLK_AHB + LPC32XX_CLK_USB_OFFSET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) /* Stub for composite clocks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) LPC32XX_CLK__NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) /* Subclocks of composite clocks, clocks above are for CCF */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) LPC32XX_CLK_PWM1_MUX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) LPC32XX_CLK_PWM1_DIV,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) LPC32XX_CLK_PWM1_GATE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) LPC32XX_CLK_PWM2_MUX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) LPC32XX_CLK_PWM2_DIV,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) LPC32XX_CLK_PWM2_GATE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) LPC32XX_CLK_UART3_MUX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) LPC32XX_CLK_UART3_DIV,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) LPC32XX_CLK_UART3_GATE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) LPC32XX_CLK_UART4_MUX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) LPC32XX_CLK_UART4_DIV,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) LPC32XX_CLK_UART4_GATE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) LPC32XX_CLK_UART5_MUX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) LPC32XX_CLK_UART5_DIV,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) LPC32XX_CLK_UART5_GATE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) LPC32XX_CLK_UART6_MUX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) LPC32XX_CLK_UART6_DIV,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) LPC32XX_CLK_UART6_GATE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) LPC32XX_CLK_TEST1_MUX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) LPC32XX_CLK_TEST1_GATE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) LPC32XX_CLK_TEST2_MUX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) LPC32XX_CLK_TEST2_GATE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) LPC32XX_CLK_USB_DIV_DIV,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) LPC32XX_CLK_USB_DIV_GATE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) LPC32XX_CLK_SD_DIV,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) LPC32XX_CLK_SD_GATE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) LPC32XX_CLK_LCD_DIV,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) LPC32XX_CLK_LCD_GATE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) LPC32XX_CLK_HW_MAX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) LPC32XX_CLK_MAX = LPC32XX_CLK_SYSCLK_ARM_MUX + 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) LPC32XX_CLK_CCF_MAX = LPC32XX_CLK_USB_AHB + 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) static struct clk *clk[LPC32XX_CLK_MAX];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) static struct clk_onecell_data clk_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) .clks = clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) .clk_num = LPC32XX_CLK_MAX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) static struct clk *usb_clk[LPC32XX_USB_CLK_MAX];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) static struct clk_onecell_data usb_clk_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) .clks = usb_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) .clk_num = LPC32XX_USB_CLK_MAX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) #define LPC32XX_CLK_PARENTS_MAX 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) struct clk_proto_t {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) const char *name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) const u8 parents[LPC32XX_CLK_PARENTS_MAX];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) u8 num_parents;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) #define CLK_PREFIX(LITERAL) LPC32XX_CLK_ ## LITERAL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) #define NUMARGS(...) (sizeof((int[]){__VA_ARGS__})/sizeof(int))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) #define LPC32XX_CLK_DEFINE(_idx, _name, _flags, ...) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) [CLK_PREFIX(_idx)] = { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) .name = _name, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) .flags = _flags, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) .parents = { __VA_ARGS__ }, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) .num_parents = NUMARGS(__VA_ARGS__), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) static const struct clk_proto_t clk_proto[LPC32XX_CLK_CCF_MAX] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) LPC32XX_CLK_DEFINE(XTAL, "xtal", 0x0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) LPC32XX_CLK_DEFINE(XTAL_32K, "xtal_32k", 0x0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) LPC32XX_CLK_DEFINE(RTC, "rtc", 0x0, LPC32XX_CLK_XTAL_32K),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) LPC32XX_CLK_DEFINE(OSC, "osc", CLK_IGNORE_UNUSED, LPC32XX_CLK_XTAL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) LPC32XX_CLK_DEFINE(SYS, "sys", CLK_IGNORE_UNUSED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) LPC32XX_CLK_OSC, LPC32XX_CLK_PLL397X),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) LPC32XX_CLK_DEFINE(PLL397X, "pll_397x", CLK_IGNORE_UNUSED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) LPC32XX_CLK_RTC),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) LPC32XX_CLK_DEFINE(HCLK_PLL, "hclk_pll", CLK_IGNORE_UNUSED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) LPC32XX_CLK_SYS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) LPC32XX_CLK_DEFINE(HCLK_DIV_PERIPH, "hclk_div_periph",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) CLK_IGNORE_UNUSED, LPC32XX_CLK_HCLK_PLL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) LPC32XX_CLK_DEFINE(HCLK_DIV, "hclk_div", CLK_IGNORE_UNUSED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) LPC32XX_CLK_HCLK_PLL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) LPC32XX_CLK_DEFINE(HCLK, "hclk", CLK_IGNORE_UNUSED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) LPC32XX_CLK_PERIPH_HCLK_MUX),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) LPC32XX_CLK_DEFINE(PERIPH, "pclk", CLK_IGNORE_UNUSED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) LPC32XX_CLK_SYSCLK_PERIPH_MUX),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) LPC32XX_CLK_DEFINE(ARM, "arm", CLK_IGNORE_UNUSED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) LPC32XX_CLK_PERIPH_ARM_MUX),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) LPC32XX_CLK_DEFINE(PERIPH_HCLK_MUX, "periph_hclk_mux",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) CLK_IGNORE_UNUSED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) LPC32XX_CLK_SYSCLK_HCLK_MUX, LPC32XX_CLK_SYSCLK_PERIPH_MUX),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) LPC32XX_CLK_DEFINE(PERIPH_ARM_MUX, "periph_arm_mux", CLK_IGNORE_UNUSED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) LPC32XX_CLK_SYSCLK_ARM_MUX, LPC32XX_CLK_SYSCLK_PERIPH_MUX),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) LPC32XX_CLK_DEFINE(SYSCLK_PERIPH_MUX, "sysclk_periph_mux",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) CLK_IGNORE_UNUSED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) LPC32XX_CLK_SYS, LPC32XX_CLK_HCLK_DIV_PERIPH),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) LPC32XX_CLK_DEFINE(SYSCLK_HCLK_MUX, "sysclk_hclk_mux",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) CLK_IGNORE_UNUSED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) LPC32XX_CLK_SYS, LPC32XX_CLK_HCLK_DIV),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) LPC32XX_CLK_DEFINE(SYSCLK_ARM_MUX, "sysclk_arm_mux", CLK_IGNORE_UNUSED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) LPC32XX_CLK_SYS, LPC32XX_CLK_HCLK_PLL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) LPC32XX_CLK_DEFINE(ARM_VFP, "vfp9", CLK_IGNORE_UNUSED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) LPC32XX_CLK_ARM),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) LPC32XX_CLK_DEFINE(USB_PLL, "usb_pll",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) CLK_SET_RATE_GATE | CLK_SET_RATE_PARENT, LPC32XX_CLK_USB_DIV),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) LPC32XX_CLK_DEFINE(USB_DIV, "usb_div", 0x0, LPC32XX_CLK_OSC),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) LPC32XX_CLK_DEFINE(USB, "usb", 0x0, LPC32XX_CLK_USB_PLL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) LPC32XX_CLK_DEFINE(DMA, "dma", 0x0, LPC32XX_CLK_HCLK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) LPC32XX_CLK_DEFINE(MLC, "mlc", 0x0, LPC32XX_CLK_HCLK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) LPC32XX_CLK_DEFINE(SLC, "slc", 0x0, LPC32XX_CLK_HCLK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) LPC32XX_CLK_DEFINE(LCD, "lcd", 0x0, LPC32XX_CLK_HCLK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) LPC32XX_CLK_DEFINE(MAC, "mac", 0x0, LPC32XX_CLK_HCLK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) LPC32XX_CLK_DEFINE(SD, "sd", 0x0, LPC32XX_CLK_ARM),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) LPC32XX_CLK_DEFINE(DDRAM, "ddram", CLK_GET_RATE_NOCACHE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) LPC32XX_CLK_SYSCLK_ARM_MUX),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) LPC32XX_CLK_DEFINE(SSP0, "ssp0", 0x0, LPC32XX_CLK_HCLK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) LPC32XX_CLK_DEFINE(SSP1, "ssp1", 0x0, LPC32XX_CLK_HCLK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) * CLK_GET_RATE_NOCACHE is needed, if UART clock is disabled, its
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) * divider register does not contain information about selected rate.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) LPC32XX_CLK_DEFINE(UART3, "uart3", CLK_GET_RATE_NOCACHE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) LPC32XX_CLK_PERIPH, LPC32XX_CLK_HCLK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) LPC32XX_CLK_DEFINE(UART4, "uart4", CLK_GET_RATE_NOCACHE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) LPC32XX_CLK_PERIPH, LPC32XX_CLK_HCLK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) LPC32XX_CLK_DEFINE(UART5, "uart5", CLK_GET_RATE_NOCACHE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) LPC32XX_CLK_PERIPH, LPC32XX_CLK_HCLK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) LPC32XX_CLK_DEFINE(UART6, "uart6", CLK_GET_RATE_NOCACHE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) LPC32XX_CLK_PERIPH, LPC32XX_CLK_HCLK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) LPC32XX_CLK_DEFINE(IRDA, "irda", 0x0, LPC32XX_CLK_PERIPH),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) LPC32XX_CLK_DEFINE(I2C1, "i2c1", 0x0, LPC32XX_CLK_HCLK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) LPC32XX_CLK_DEFINE(I2C2, "i2c2", 0x0, LPC32XX_CLK_HCLK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) LPC32XX_CLK_DEFINE(TIMER0, "timer0", 0x0, LPC32XX_CLK_PERIPH),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) LPC32XX_CLK_DEFINE(TIMER1, "timer1", 0x0, LPC32XX_CLK_PERIPH),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) LPC32XX_CLK_DEFINE(TIMER2, "timer2", 0x0, LPC32XX_CLK_PERIPH),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) LPC32XX_CLK_DEFINE(TIMER3, "timer3", 0x0, LPC32XX_CLK_PERIPH),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) LPC32XX_CLK_DEFINE(TIMER4, "timer4", 0x0, LPC32XX_CLK_PERIPH),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) LPC32XX_CLK_DEFINE(TIMER5, "timer5", 0x0, LPC32XX_CLK_PERIPH),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) LPC32XX_CLK_DEFINE(WDOG, "watchdog", 0x0, LPC32XX_CLK_PERIPH),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) LPC32XX_CLK_DEFINE(I2S0, "i2s0", 0x0, LPC32XX_CLK_HCLK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) LPC32XX_CLK_DEFINE(I2S1, "i2s1", 0x0, LPC32XX_CLK_HCLK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) LPC32XX_CLK_DEFINE(SPI1, "spi1", 0x0, LPC32XX_CLK_HCLK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) LPC32XX_CLK_DEFINE(SPI2, "spi2", 0x0, LPC32XX_CLK_HCLK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) LPC32XX_CLK_DEFINE(MCPWM, "mcpwm", 0x0, LPC32XX_CLK_HCLK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) LPC32XX_CLK_DEFINE(HSTIMER, "hstimer", 0x0, LPC32XX_CLK_PERIPH),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) LPC32XX_CLK_DEFINE(KEY, "key", 0x0, LPC32XX_CLK_RTC),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) LPC32XX_CLK_DEFINE(PWM1, "pwm1", 0x0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) LPC32XX_CLK_RTC, LPC32XX_CLK_PERIPH),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) LPC32XX_CLK_DEFINE(PWM2, "pwm2", 0x0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) LPC32XX_CLK_RTC, LPC32XX_CLK_PERIPH),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) LPC32XX_CLK_DEFINE(ADC, "adc", 0x0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) LPC32XX_CLK_ADC_RTC, LPC32XX_CLK_ADC_DIV),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) LPC32XX_CLK_DEFINE(ADC_DIV, "adc_div", 0x0, LPC32XX_CLK_PERIPH),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) LPC32XX_CLK_DEFINE(ADC_RTC, "adc_rtc", 0x0, LPC32XX_CLK_RTC),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) LPC32XX_CLK_DEFINE(TEST1, "test1", 0x0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) LPC32XX_CLK_PERIPH, LPC32XX_CLK_RTC, LPC32XX_CLK_OSC),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) LPC32XX_CLK_DEFINE(TEST2, "test2", 0x0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) LPC32XX_CLK_HCLK, LPC32XX_CLK_PERIPH, LPC32XX_CLK_USB,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) LPC32XX_CLK_OSC, LPC32XX_CLK_PLL397X),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) /* USB controller clocks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) LPC32XX_CLK_DEFINE(USB_AHB, "usb_ahb", 0x0, LPC32XX_CLK_USB),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) LPC32XX_CLK_DEFINE(USB_OTG, "usb_otg", 0x0, LPC32XX_CLK_USB_AHB),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) LPC32XX_CLK_DEFINE(USB_I2C, "usb_i2c", 0x0, LPC32XX_CLK_USB_AHB),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) LPC32XX_CLK_DEFINE(USB_DEV, "usb_dev", 0x0, LPC32XX_CLK_USB_OTG),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) LPC32XX_CLK_DEFINE(USB_HOST, "usb_host", 0x0, LPC32XX_CLK_USB_OTG),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) struct lpc32xx_clk {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) struct clk_hw hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) u32 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) u32 enable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) u32 enable_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) u32 disable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) u32 disable_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) u32 busy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) u32 busy_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) enum clk_pll_mode {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) PLL_UNKNOWN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) PLL_DIRECT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) PLL_BYPASS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) PLL_DIRECT_BYPASS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) PLL_INTEGER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) PLL_NON_INTEGER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) struct lpc32xx_pll_clk {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) struct clk_hw hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) u32 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) u32 enable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) unsigned long m_div;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) unsigned long n_div;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) unsigned long p_div;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) enum clk_pll_mode mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) struct lpc32xx_usb_clk {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) struct clk_hw hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) u32 ctrl_enable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) u32 ctrl_disable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) u32 ctrl_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) u32 enable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) u32 busy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) struct lpc32xx_clk_mux {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) struct clk_hw hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) u32 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) u32 mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) u8 shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) u32 *table;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) u8 flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) struct lpc32xx_clk_div {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) struct clk_hw hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) u32 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) u8 shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) u8 width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) const struct clk_div_table *table;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) u8 flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) struct lpc32xx_clk_gate {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) struct clk_hw hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) u32 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) u8 bit_idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) u8 flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) #define to_lpc32xx_clk(_hw) container_of(_hw, struct lpc32xx_clk, hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) #define to_lpc32xx_pll_clk(_hw) container_of(_hw, struct lpc32xx_pll_clk, hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) #define to_lpc32xx_usb_clk(_hw) container_of(_hw, struct lpc32xx_usb_clk, hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) #define to_lpc32xx_mux(_hw) container_of(_hw, struct lpc32xx_clk_mux, hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) #define to_lpc32xx_div(_hw) container_of(_hw, struct lpc32xx_clk_div, hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) #define to_lpc32xx_gate(_hw) container_of(_hw, struct lpc32xx_clk_gate, hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) static inline bool pll_is_valid(u64 val0, u64 val1, u64 min, u64 max)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) return (val0 >= (val1 * min) && val0 <= (val1 * max));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) static inline u32 lpc32xx_usb_clk_read(struct lpc32xx_usb_clk *clk)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) return readl(usb_clk_vbase + LPC32XX_USB_CLK_STS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) static inline void lpc32xx_usb_clk_write(struct lpc32xx_usb_clk *clk, u32 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) writel(val, usb_clk_vbase + LPC32XX_USB_CLK_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) static int clk_mask_enable(struct clk_hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) struct lpc32xx_clk *clk = to_lpc32xx_clk(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) regmap_read(clk_regmap, clk->reg, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) if (clk->busy_mask && (val & clk->busy_mask) == clk->busy)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) return -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) return regmap_update_bits(clk_regmap, clk->reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) clk->enable_mask, clk->enable);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) static void clk_mask_disable(struct clk_hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) struct lpc32xx_clk *clk = to_lpc32xx_clk(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) regmap_update_bits(clk_regmap, clk->reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) clk->disable_mask, clk->disable);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) static int clk_mask_is_enabled(struct clk_hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) struct lpc32xx_clk *clk = to_lpc32xx_clk(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) regmap_read(clk_regmap, clk->reg, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) return ((val & clk->enable_mask) == clk->enable);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) static const struct clk_ops clk_mask_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) .enable = clk_mask_enable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) .disable = clk_mask_disable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) .is_enabled = clk_mask_is_enabled,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) static int clk_pll_enable(struct clk_hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) struct lpc32xx_pll_clk *clk = to_lpc32xx_pll_clk(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) u32 val, count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) regmap_update_bits(clk_regmap, clk->reg, clk->enable, clk->enable);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) for (count = 0; count < 1000; count++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) regmap_read(clk_regmap, clk->reg, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) if (val & PLL_CTRL_LOCK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) if (val & PLL_CTRL_LOCK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) return -ETIMEDOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) static void clk_pll_disable(struct clk_hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) struct lpc32xx_pll_clk *clk = to_lpc32xx_pll_clk(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) regmap_update_bits(clk_regmap, clk->reg, clk->enable, 0x0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) static int clk_pll_is_enabled(struct clk_hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) struct lpc32xx_pll_clk *clk = to_lpc32xx_pll_clk(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) regmap_read(clk_regmap, clk->reg, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) val &= clk->enable | PLL_CTRL_LOCK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) if (val == (clk->enable | PLL_CTRL_LOCK))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) static unsigned long clk_pll_397x_recalc_rate(struct clk_hw *hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) unsigned long parent_rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) return parent_rate * 397;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) static unsigned long clk_pll_recalc_rate(struct clk_hw *hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) unsigned long parent_rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) struct lpc32xx_pll_clk *clk = to_lpc32xx_pll_clk(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) bool is_direct, is_bypass, is_feedback;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) unsigned long rate, cco_rate, ref_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) regmap_read(clk_regmap, clk->reg, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) is_direct = val & PLL_CTRL_DIRECT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) is_bypass = val & PLL_CTRL_BYPASS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) is_feedback = val & PLL_CTRL_FEEDBACK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) clk->m_div = ((val & PLL_CTRL_FEEDDIV) >> 1) + 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) clk->n_div = ((val & PLL_CTRL_PREDIV) >> 9) + 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) clk->p_div = ((val & PLL_CTRL_POSTDIV) >> 11) + 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) if (is_direct && is_bypass) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) clk->p_div = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) clk->mode = PLL_DIRECT_BYPASS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) return parent_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) if (is_bypass) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) clk->mode = PLL_BYPASS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) return parent_rate / (1 << clk->p_div);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) if (is_direct) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) clk->p_div = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) clk->mode = PLL_DIRECT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) ref_rate = parent_rate / clk->n_div;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) rate = cco_rate = ref_rate * clk->m_div;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) if (!is_direct) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) if (is_feedback) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) cco_rate *= (1 << clk->p_div);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) clk->mode = PLL_INTEGER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) rate /= (1 << clk->p_div);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) clk->mode = PLL_NON_INTEGER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) pr_debug("%s: %lu: 0x%x: %d/%d/%d, %lu/%lu/%d => %lu\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) clk_hw_get_name(hw),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) parent_rate, val, is_direct, is_bypass, is_feedback,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) clk->n_div, clk->m_div, (1 << clk->p_div), rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) if (clk_pll_is_enabled(hw) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) !(pll_is_valid(parent_rate, 1, 1000000, 20000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) && pll_is_valid(cco_rate, 1, 156000000, 320000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) && pll_is_valid(ref_rate, 1, 1000000, 27000000)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) pr_err("%s: PLL clocks are not in valid ranges: %lu/%lu/%lu\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) clk_hw_get_name(hw),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) parent_rate, cco_rate, ref_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) return rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) static int clk_pll_set_rate(struct clk_hw *hw, unsigned long rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) unsigned long parent_rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) struct lpc32xx_pll_clk *clk = to_lpc32xx_pll_clk(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) unsigned long new_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) /* Validate PLL clock parameters computed on round rate stage */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) switch (clk->mode) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) case PLL_DIRECT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) val = PLL_CTRL_DIRECT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) val |= (clk->m_div - 1) << 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) val |= (clk->n_div - 1) << 9;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) new_rate = (parent_rate * clk->m_div) / clk->n_div;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) case PLL_BYPASS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) val = PLL_CTRL_BYPASS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) val |= (clk->p_div - 1) << 11;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) new_rate = parent_rate / (1 << (clk->p_div));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) case PLL_DIRECT_BYPASS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) val = PLL_CTRL_DIRECT | PLL_CTRL_BYPASS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) new_rate = parent_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) case PLL_INTEGER:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) val = PLL_CTRL_FEEDBACK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) val |= (clk->m_div - 1) << 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) val |= (clk->n_div - 1) << 9;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) val |= (clk->p_div - 1) << 11;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) new_rate = (parent_rate * clk->m_div) / clk->n_div;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) case PLL_NON_INTEGER:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) val = 0x0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) val |= (clk->m_div - 1) << 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) val |= (clk->n_div - 1) << 9;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) val |= (clk->p_div - 1) << 11;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) new_rate = (parent_rate * clk->m_div) /
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) (clk->n_div * (1 << clk->p_div));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) /* Sanity check that round rate is equal to the requested one */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) if (new_rate != rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) return regmap_update_bits(clk_regmap, clk->reg, 0x1FFFF, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) static long clk_hclk_pll_round_rate(struct clk_hw *hw, unsigned long rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) unsigned long *parent_rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) struct lpc32xx_pll_clk *clk = to_lpc32xx_pll_clk(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) u64 m_i, o = rate, i = *parent_rate, d = (u64)rate << 6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) u64 m = 0, n = 0, p = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) int p_i, n_i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) pr_debug("%s: %lu/%lu\n", clk_hw_get_name(hw), *parent_rate, rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) if (rate > 266500000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) /* Have to check all 20 possibilities to find the minimal M */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) for (p_i = 4; p_i >= 0; p_i--) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) for (n_i = 4; n_i > 0; n_i--) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) m_i = div64_u64(o * n_i * (1 << p_i), i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) /* Check for valid PLL parameter constraints */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) if (!(m_i && m_i <= 256
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) && pll_is_valid(i, n_i, 1000000, 27000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) && pll_is_valid(i * m_i * (1 << p_i), n_i,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) 156000000, 320000000)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) /* Store some intermediate valid parameters */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) if (o * n_i * (1 << p_i) - i * m_i <= d) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) m = m_i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) n = n_i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) p = p_i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) d = o * n_i * (1 << p_i) - i * m_i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) if (d == (u64)rate << 6) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) pr_err("%s: %lu: no valid PLL parameters are found\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) clk_hw_get_name(hw), rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) clk->m_div = m;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) clk->n_div = n;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) clk->p_div = p;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) /* Set only direct or non-integer mode of PLL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) if (!p)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) clk->mode = PLL_DIRECT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) clk->mode = PLL_NON_INTEGER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) o = div64_u64(i * m, n * (1 << p));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) if (!d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) pr_debug("%s: %lu: found exact match: %llu/%llu/%llu\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) clk_hw_get_name(hw), rate, m, n, p);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) pr_debug("%s: %lu: found closest: %llu/%llu/%llu - %llu\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) clk_hw_get_name(hw), rate, m, n, p, o);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) return o;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) static long clk_usb_pll_round_rate(struct clk_hw *hw, unsigned long rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) unsigned long *parent_rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) struct lpc32xx_pll_clk *clk = to_lpc32xx_pll_clk(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) struct clk_hw *usb_div_hw, *osc_hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) u64 d_i, n_i, m, o;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) pr_debug("%s: %lu/%lu\n", clk_hw_get_name(hw), *parent_rate, rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) * The only supported USB clock is 48MHz, with PLL internal constraints
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) * on Fclkin, Fcco and Fref this implies that Fcco must be 192MHz
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) * and post-divider must be 4, this slightly simplifies calculation of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) * USB divider, USB PLL N and M parameters.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) if (rate != 48000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) /* USB divider clock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) usb_div_hw = clk_hw_get_parent_by_index(hw, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) if (!usb_div_hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) /* Main oscillator clock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) osc_hw = clk_hw_get_parent_by_index(usb_div_hw, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) if (!osc_hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) o = clk_hw_get_rate(osc_hw); /* must be in range 1..20 MHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) /* Check if valid USB divider and USB PLL parameters exists */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) for (d_i = 16; d_i >= 1; d_i--) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) for (n_i = 1; n_i <= 4; n_i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) m = div64_u64(192000000 * d_i * n_i, o);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) if (!(m && m <= 256
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) && m * o == 192000000 * d_i * n_i
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) && pll_is_valid(o, d_i, 1000000, 20000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) && pll_is_valid(o, d_i * n_i, 1000000, 27000000)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) clk->n_div = n_i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) clk->m_div = m;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) clk->p_div = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) clk->mode = PLL_NON_INTEGER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) *parent_rate = div64_u64(o, d_i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) return rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) #define LPC32XX_DEFINE_PLL_OPS(_name, _rc, _sr, _rr) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) static const struct clk_ops clk_ ##_name ## _ops = { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) .enable = clk_pll_enable, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) .disable = clk_pll_disable, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) .is_enabled = clk_pll_is_enabled, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) .recalc_rate = _rc, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) .set_rate = _sr, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) .round_rate = _rr, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) LPC32XX_DEFINE_PLL_OPS(pll_397x, clk_pll_397x_recalc_rate, NULL, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) LPC32XX_DEFINE_PLL_OPS(hclk_pll, clk_pll_recalc_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) clk_pll_set_rate, clk_hclk_pll_round_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) LPC32XX_DEFINE_PLL_OPS(usb_pll, clk_pll_recalc_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) clk_pll_set_rate, clk_usb_pll_round_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) static int clk_ddram_is_enabled(struct clk_hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) struct lpc32xx_clk *clk = to_lpc32xx_clk(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) regmap_read(clk_regmap, clk->reg, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) val &= clk->enable_mask | clk->busy_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) return (val == (BIT(7) | BIT(0)) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) val == (BIT(8) | BIT(1)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) static int clk_ddram_enable(struct clk_hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) struct lpc32xx_clk *clk = to_lpc32xx_clk(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) u32 val, hclk_div;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) regmap_read(clk_regmap, clk->reg, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) hclk_div = val & clk->busy_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) * DDRAM clock must be 2 times higher than HCLK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) * this implies DDRAM clock can not be enabled,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) * if HCLK clock rate is equal to ARM clock rate
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) if (hclk_div == 0x0 || hclk_div == (BIT(1) | BIT(0)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) return regmap_update_bits(clk_regmap, clk->reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) clk->enable_mask, hclk_div << 7);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) static unsigned long clk_ddram_recalc_rate(struct clk_hw *hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) unsigned long parent_rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) struct lpc32xx_clk *clk = to_lpc32xx_clk(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) if (!clk_ddram_is_enabled(hw))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) regmap_read(clk_regmap, clk->reg, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) val &= clk->enable_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) return parent_rate / (val >> 7);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) static const struct clk_ops clk_ddram_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) .enable = clk_ddram_enable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) .disable = clk_mask_disable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) .is_enabled = clk_ddram_is_enabled,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) .recalc_rate = clk_ddram_recalc_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) static unsigned long lpc32xx_clk_uart_recalc_rate(struct clk_hw *hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) unsigned long parent_rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) struct lpc32xx_clk *clk = to_lpc32xx_clk(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) u32 val, x, y;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) regmap_read(clk_regmap, clk->reg, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) x = (val & 0xFF00) >> 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) y = val & 0xFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) if (x && y)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) return (parent_rate * x) / y;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) static const struct clk_ops lpc32xx_uart_div_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) .recalc_rate = lpc32xx_clk_uart_recalc_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) static const struct clk_div_table clk_hclk_div_table[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) { .val = 0, .div = 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) { .val = 1, .div = 2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) { .val = 2, .div = 4 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) { },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) static u32 test1_mux_table[] = { 0, 1, 2, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) static u32 test2_mux_table[] = { 0, 1, 2, 5, 7, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) static int clk_usb_enable(struct clk_hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) struct lpc32xx_usb_clk *clk = to_lpc32xx_usb_clk(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) u32 val, ctrl_val, count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) pr_debug("%s: 0x%x\n", clk_hw_get_name(hw), clk->enable);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) if (clk->ctrl_mask) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) regmap_read(clk_regmap, LPC32XX_CLKPWR_USB_CTRL, &ctrl_val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) regmap_update_bits(clk_regmap, LPC32XX_CLKPWR_USB_CTRL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) clk->ctrl_mask, clk->ctrl_enable);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) val = lpc32xx_usb_clk_read(clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) if (clk->busy && (val & clk->busy) == clk->busy) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) if (clk->ctrl_mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) regmap_write(clk_regmap, LPC32XX_CLKPWR_USB_CTRL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) ctrl_val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) return -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) val |= clk->enable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) lpc32xx_usb_clk_write(clk, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) for (count = 0; count < 1000; count++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) val = lpc32xx_usb_clk_read(clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) if ((val & clk->enable) == clk->enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) if ((val & clk->enable) == clk->enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) if (clk->ctrl_mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) regmap_write(clk_regmap, LPC32XX_CLKPWR_USB_CTRL, ctrl_val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) return -ETIMEDOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) static void clk_usb_disable(struct clk_hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) struct lpc32xx_usb_clk *clk = to_lpc32xx_usb_clk(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) u32 val = lpc32xx_usb_clk_read(clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) val &= ~clk->enable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) lpc32xx_usb_clk_write(clk, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) if (clk->ctrl_mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) regmap_update_bits(clk_regmap, LPC32XX_CLKPWR_USB_CTRL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) clk->ctrl_mask, clk->ctrl_disable);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) static int clk_usb_is_enabled(struct clk_hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) struct lpc32xx_usb_clk *clk = to_lpc32xx_usb_clk(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) u32 ctrl_val, val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) if (clk->ctrl_mask) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) regmap_read(clk_regmap, LPC32XX_CLKPWR_USB_CTRL, &ctrl_val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) if ((ctrl_val & clk->ctrl_mask) != clk->ctrl_enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) val = lpc32xx_usb_clk_read(clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) return ((val & clk->enable) == clk->enable);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) static unsigned long clk_usb_i2c_recalc_rate(struct clk_hw *hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) unsigned long parent_rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) return clk_get_rate(clk[LPC32XX_CLK_PERIPH]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) static const struct clk_ops clk_usb_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) .enable = clk_usb_enable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) .disable = clk_usb_disable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) .is_enabled = clk_usb_is_enabled,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) static const struct clk_ops clk_usb_i2c_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) .enable = clk_usb_enable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) .disable = clk_usb_disable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) .is_enabled = clk_usb_is_enabled,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) .recalc_rate = clk_usb_i2c_recalc_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) static int lpc32xx_clk_gate_enable(struct clk_hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) struct lpc32xx_clk_gate *clk = to_lpc32xx_gate(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) u32 mask = BIT(clk->bit_idx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) u32 val = (clk->flags & CLK_GATE_SET_TO_DISABLE ? 0x0 : mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) return regmap_update_bits(clk_regmap, clk->reg, mask, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) static void lpc32xx_clk_gate_disable(struct clk_hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) struct lpc32xx_clk_gate *clk = to_lpc32xx_gate(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) u32 mask = BIT(clk->bit_idx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) u32 val = (clk->flags & CLK_GATE_SET_TO_DISABLE ? mask : 0x0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) regmap_update_bits(clk_regmap, clk->reg, mask, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) static int lpc32xx_clk_gate_is_enabled(struct clk_hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) struct lpc32xx_clk_gate *clk = to_lpc32xx_gate(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) bool is_set;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) regmap_read(clk_regmap, clk->reg, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) is_set = val & BIT(clk->bit_idx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) return (clk->flags & CLK_GATE_SET_TO_DISABLE ? !is_set : is_set);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) static const struct clk_ops lpc32xx_clk_gate_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) .enable = lpc32xx_clk_gate_enable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) .disable = lpc32xx_clk_gate_disable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) .is_enabled = lpc32xx_clk_gate_is_enabled,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) #define div_mask(width) ((1 << (width)) - 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) static unsigned int _get_table_div(const struct clk_div_table *table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) unsigned int val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) const struct clk_div_table *clkt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) for (clkt = table; clkt->div; clkt++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) if (clkt->val == val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) return clkt->div;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) static unsigned int _get_div(const struct clk_div_table *table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) unsigned int val, unsigned long flags, u8 width)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) if (flags & CLK_DIVIDER_ONE_BASED)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) return val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) if (table)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) return _get_table_div(table, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) return val + 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) static unsigned long clk_divider_recalc_rate(struct clk_hw *hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) unsigned long parent_rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) struct lpc32xx_clk_div *divider = to_lpc32xx_div(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) unsigned int val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) regmap_read(clk_regmap, divider->reg, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) val >>= divider->shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) val &= div_mask(divider->width);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) return divider_recalc_rate(hw, parent_rate, val, divider->table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) divider->flags, divider->width);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) static long clk_divider_round_rate(struct clk_hw *hw, unsigned long rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) unsigned long *prate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) struct lpc32xx_clk_div *divider = to_lpc32xx_div(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) unsigned int bestdiv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) /* if read only, just return current value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) if (divider->flags & CLK_DIVIDER_READ_ONLY) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) regmap_read(clk_regmap, divider->reg, &bestdiv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) bestdiv >>= divider->shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) bestdiv &= div_mask(divider->width);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) bestdiv = _get_div(divider->table, bestdiv, divider->flags,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) divider->width);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) return DIV_ROUND_UP(*prate, bestdiv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) return divider_round_rate(hw, rate, prate, divider->table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) divider->width, divider->flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) static int clk_divider_set_rate(struct clk_hw *hw, unsigned long rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) unsigned long parent_rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) struct lpc32xx_clk_div *divider = to_lpc32xx_div(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) unsigned int value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) value = divider_get_val(rate, parent_rate, divider->table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) divider->width, divider->flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) return regmap_update_bits(clk_regmap, divider->reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) div_mask(divider->width) << divider->shift,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) value << divider->shift);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) static const struct clk_ops lpc32xx_clk_divider_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) .recalc_rate = clk_divider_recalc_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) .round_rate = clk_divider_round_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) .set_rate = clk_divider_set_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) static u8 clk_mux_get_parent(struct clk_hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) struct lpc32xx_clk_mux *mux = to_lpc32xx_mux(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) u32 num_parents = clk_hw_get_num_parents(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) regmap_read(clk_regmap, mux->reg, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) val >>= mux->shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) val &= mux->mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) if (mux->table) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) u32 i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) for (i = 0; i < num_parents; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) if (mux->table[i] == val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) return i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) if (val >= num_parents)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) return val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) static int clk_mux_set_parent(struct clk_hw *hw, u8 index)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) struct lpc32xx_clk_mux *mux = to_lpc32xx_mux(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) if (mux->table)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) index = mux->table[index];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) return regmap_update_bits(clk_regmap, mux->reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) mux->mask << mux->shift, index << mux->shift);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) static const struct clk_ops lpc32xx_clk_mux_ro_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) .get_parent = clk_mux_get_parent,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) static const struct clk_ops lpc32xx_clk_mux_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) .get_parent = clk_mux_get_parent,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) .set_parent = clk_mux_set_parent,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) .determine_rate = __clk_mux_determine_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) enum lpc32xx_clk_type {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) CLK_FIXED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) CLK_MUX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) CLK_DIV,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) CLK_GATE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) CLK_COMPOSITE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) CLK_LPC32XX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) CLK_LPC32XX_PLL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) CLK_LPC32XX_USB,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) struct clk_hw_proto0 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) const struct clk_ops *ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) union {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) struct lpc32xx_pll_clk pll;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) struct lpc32xx_clk clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) struct lpc32xx_usb_clk usb_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) struct lpc32xx_clk_mux mux;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) struct lpc32xx_clk_div div;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) struct lpc32xx_clk_gate gate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) struct clk_hw_proto1 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) struct clk_hw_proto0 *mux;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) struct clk_hw_proto0 *div;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) struct clk_hw_proto0 *gate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) struct clk_hw_proto {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) enum lpc32xx_clk_type type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) union {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) struct clk_fixed_rate f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) struct clk_hw_proto0 hw0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) struct clk_hw_proto1 hw1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) #define LPC32XX_DEFINE_FIXED(_idx, _rate) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) [CLK_PREFIX(_idx)] = { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) .type = CLK_FIXED, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) .f = { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) .fixed_rate = (_rate), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) }, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090) }, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) #define LPC32XX_DEFINE_PLL(_idx, _name, _reg, _enable) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) [CLK_PREFIX(_idx)] = { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) .type = CLK_LPC32XX_PLL, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097) .hw0 = { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) .ops = &clk_ ##_name ## _ops, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100) .pll = { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) .reg = LPC32XX_CLKPWR_ ## _reg, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) .enable = (_enable), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103) }, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104) }, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) }, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106) }, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) #define LPC32XX_DEFINE_MUX(_idx, _reg, _shift, _mask, _table, _flags) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) [CLK_PREFIX(_idx)] = { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) .type = CLK_MUX, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113) .hw0 = { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114) .ops = (_flags & CLK_MUX_READ_ONLY ? \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115) &lpc32xx_clk_mux_ro_ops : \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) &lpc32xx_clk_mux_ops), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118) .mux = { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119) .reg = LPC32XX_CLKPWR_ ## _reg, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120) .mask = (_mask), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121) .shift = (_shift), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122) .table = (_table), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123) .flags = (_flags), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124) }, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125) }, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) }, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127) }, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130) #define LPC32XX_DEFINE_DIV(_idx, _reg, _shift, _width, _table, _flags) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131) [CLK_PREFIX(_idx)] = { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132) .type = CLK_DIV, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134) .hw0 = { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135) .ops = &lpc32xx_clk_divider_ops, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137) .div = { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138) .reg = LPC32XX_CLKPWR_ ## _reg, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139) .shift = (_shift), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140) .width = (_width), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141) .table = (_table), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142) .flags = (_flags), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143) }, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144) }, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145) }, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146) }, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149) #define LPC32XX_DEFINE_GATE(_idx, _reg, _bit, _flags) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150) [CLK_PREFIX(_idx)] = { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151) .type = CLK_GATE, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153) .hw0 = { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154) .ops = &lpc32xx_clk_gate_ops, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156) .gate = { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157) .reg = LPC32XX_CLKPWR_ ## _reg, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158) .bit_idx = (_bit), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159) .flags = (_flags), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160) }, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161) }, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162) }, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163) }, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166) #define LPC32XX_DEFINE_CLK(_idx, _reg, _e, _em, _d, _dm, _b, _bm, _ops) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167) [CLK_PREFIX(_idx)] = { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168) .type = CLK_LPC32XX, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170) .hw0 = { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171) .ops = &(_ops), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173) .clk = { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174) .reg = LPC32XX_CLKPWR_ ## _reg, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175) .enable = (_e), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176) .enable_mask = (_em), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177) .disable = (_d), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178) .disable_mask = (_dm), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179) .busy = (_b), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180) .busy_mask = (_bm), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181) }, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182) }, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183) }, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184) }, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187) #define LPC32XX_DEFINE_USB(_idx, _ce, _cd, _cm, _e, _b, _ops) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188) [CLK_PREFIX(_idx)] = { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189) .type = CLK_LPC32XX_USB, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191) .hw0 = { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192) .ops = &(_ops), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194) .usb_clk = { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195) .ctrl_enable = (_ce), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196) .ctrl_disable = (_cd), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197) .ctrl_mask = (_cm), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198) .enable = (_e), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199) .busy = (_b), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200) } \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201) }, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202) } \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203) }, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206) #define LPC32XX_DEFINE_COMPOSITE(_idx, _mux, _div, _gate) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207) [CLK_PREFIX(_idx)] = { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208) .type = CLK_COMPOSITE, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210) .hw1 = { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211) .mux = (CLK_PREFIX(_mux) == LPC32XX_CLK__NULL ? NULL : \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212) &clk_hw_proto[CLK_PREFIX(_mux)].hw0), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213) .div = (CLK_PREFIX(_div) == LPC32XX_CLK__NULL ? NULL : \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214) &clk_hw_proto[CLK_PREFIX(_div)].hw0), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215) .gate = (CLK_PREFIX(_gate) == LPC32XX_CLK__NULL ? NULL :\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216) &clk_hw_proto[CLK_PREFIX(_gate)].hw0), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217) }, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218) }, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221) static struct clk_hw_proto clk_hw_proto[LPC32XX_CLK_HW_MAX] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222) LPC32XX_DEFINE_FIXED(RTC, 32768),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223) LPC32XX_DEFINE_PLL(PLL397X, pll_397x, HCLKPLL_CTRL, BIT(1)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224) LPC32XX_DEFINE_PLL(HCLK_PLL, hclk_pll, HCLKPLL_CTRL, PLL_CTRL_ENABLE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225) LPC32XX_DEFINE_PLL(USB_PLL, usb_pll, USB_CTRL, PLL_CTRL_ENABLE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226) LPC32XX_DEFINE_GATE(OSC, OSC_CTRL, 0, CLK_GATE_SET_TO_DISABLE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227) LPC32XX_DEFINE_GATE(USB, USB_CTRL, 18, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229) LPC32XX_DEFINE_DIV(HCLK_DIV_PERIPH, HCLKDIV_CTRL, 2, 5, NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230) CLK_DIVIDER_READ_ONLY),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231) LPC32XX_DEFINE_DIV(HCLK_DIV, HCLKDIV_CTRL, 0, 2, clk_hclk_div_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232) CLK_DIVIDER_READ_ONLY),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234) /* Register 3 read-only muxes with a single control PWR_CTRL[2] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235) LPC32XX_DEFINE_MUX(SYSCLK_PERIPH_MUX, PWR_CTRL, 2, 0x1, NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236) CLK_MUX_READ_ONLY),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237) LPC32XX_DEFINE_MUX(SYSCLK_HCLK_MUX, PWR_CTRL, 2, 0x1, NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238) CLK_MUX_READ_ONLY),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239) LPC32XX_DEFINE_MUX(SYSCLK_ARM_MUX, PWR_CTRL, 2, 0x1, NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240) CLK_MUX_READ_ONLY),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241) /* Register 2 read-only muxes with a single control PWR_CTRL[10] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242) LPC32XX_DEFINE_MUX(PERIPH_HCLK_MUX, PWR_CTRL, 10, 0x1, NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243) CLK_MUX_READ_ONLY),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244) LPC32XX_DEFINE_MUX(PERIPH_ARM_MUX, PWR_CTRL, 10, 0x1, NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245) CLK_MUX_READ_ONLY),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247) /* 3 always on gates with a single control PWR_CTRL[0] same as OSC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1248) LPC32XX_DEFINE_GATE(PERIPH, PWR_CTRL, 0, CLK_GATE_SET_TO_DISABLE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1249) LPC32XX_DEFINE_GATE(HCLK, PWR_CTRL, 0, CLK_GATE_SET_TO_DISABLE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1250) LPC32XX_DEFINE_GATE(ARM, PWR_CTRL, 0, CLK_GATE_SET_TO_DISABLE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1251)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1252) LPC32XX_DEFINE_GATE(ARM_VFP, DEBUG_CTRL, 4, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1253) LPC32XX_DEFINE_GATE(DMA, DMA_CLK_CTRL, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1254) LPC32XX_DEFINE_CLK(DDRAM, HCLKDIV_CTRL, 0x0, BIT(8) | BIT(7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1255) 0x0, BIT(8) | BIT(7), 0x0, BIT(1) | BIT(0), clk_ddram_ops),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1256)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1257) LPC32XX_DEFINE_GATE(TIMER0, TIMCLK_CTRL1, 2, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1258) LPC32XX_DEFINE_GATE(TIMER1, TIMCLK_CTRL1, 3, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1259) LPC32XX_DEFINE_GATE(TIMER2, TIMCLK_CTRL1, 4, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1260) LPC32XX_DEFINE_GATE(TIMER3, TIMCLK_CTRL1, 5, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1261) LPC32XX_DEFINE_GATE(TIMER4, TIMCLK_CTRL1, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1262) LPC32XX_DEFINE_GATE(TIMER5, TIMCLK_CTRL1, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1263)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1264) LPC32XX_DEFINE_GATE(SSP0, SSP_CTRL, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1265) LPC32XX_DEFINE_GATE(SSP1, SSP_CTRL, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1266) LPC32XX_DEFINE_GATE(SPI1, SPI_CTRL, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1267) LPC32XX_DEFINE_GATE(SPI2, SPI_CTRL, 4, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1268) LPC32XX_DEFINE_GATE(I2S0, I2S_CTRL, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1269) LPC32XX_DEFINE_GATE(I2S1, I2S_CTRL, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1270) LPC32XX_DEFINE_GATE(I2C1, I2CCLK_CTRL, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1271) LPC32XX_DEFINE_GATE(I2C2, I2CCLK_CTRL, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1272) LPC32XX_DEFINE_GATE(WDOG, TIMCLK_CTRL, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1273) LPC32XX_DEFINE_GATE(HSTIMER, TIMCLK_CTRL, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1274)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1275) LPC32XX_DEFINE_GATE(KEY, KEYCLK_CTRL, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1276) LPC32XX_DEFINE_GATE(MCPWM, TIMCLK_CTRL1, 6, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1277)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1278) LPC32XX_DEFINE_MUX(PWM1_MUX, PWMCLK_CTRL, 1, 0x1, NULL, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1279) LPC32XX_DEFINE_DIV(PWM1_DIV, PWMCLK_CTRL, 4, 4, NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1280) CLK_DIVIDER_ONE_BASED),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1281) LPC32XX_DEFINE_GATE(PWM1_GATE, PWMCLK_CTRL, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1282) LPC32XX_DEFINE_COMPOSITE(PWM1, PWM1_MUX, PWM1_DIV, PWM1_GATE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1283)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1284) LPC32XX_DEFINE_MUX(PWM2_MUX, PWMCLK_CTRL, 3, 0x1, NULL, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1285) LPC32XX_DEFINE_DIV(PWM2_DIV, PWMCLK_CTRL, 8, 4, NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1286) CLK_DIVIDER_ONE_BASED),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1287) LPC32XX_DEFINE_GATE(PWM2_GATE, PWMCLK_CTRL, 2, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1288) LPC32XX_DEFINE_COMPOSITE(PWM2, PWM2_MUX, PWM2_DIV, PWM2_GATE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1289)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1290) LPC32XX_DEFINE_MUX(UART3_MUX, UART3_CLK_CTRL, 16, 0x1, NULL, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1291) LPC32XX_DEFINE_CLK(UART3_DIV, UART3_CLK_CTRL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1292) 0, 0, 0, 0, 0, 0, lpc32xx_uart_div_ops),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1293) LPC32XX_DEFINE_GATE(UART3_GATE, UART_CLK_CTRL, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1294) LPC32XX_DEFINE_COMPOSITE(UART3, UART3_MUX, UART3_DIV, UART3_GATE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1295)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1296) LPC32XX_DEFINE_MUX(UART4_MUX, UART4_CLK_CTRL, 16, 0x1, NULL, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1297) LPC32XX_DEFINE_CLK(UART4_DIV, UART4_CLK_CTRL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1298) 0, 0, 0, 0, 0, 0, lpc32xx_uart_div_ops),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1299) LPC32XX_DEFINE_GATE(UART4_GATE, UART_CLK_CTRL, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1300) LPC32XX_DEFINE_COMPOSITE(UART4, UART4_MUX, UART4_DIV, UART4_GATE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1301)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1302) LPC32XX_DEFINE_MUX(UART5_MUX, UART5_CLK_CTRL, 16, 0x1, NULL, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1303) LPC32XX_DEFINE_CLK(UART5_DIV, UART5_CLK_CTRL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1304) 0, 0, 0, 0, 0, 0, lpc32xx_uart_div_ops),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1305) LPC32XX_DEFINE_GATE(UART5_GATE, UART_CLK_CTRL, 2, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1306) LPC32XX_DEFINE_COMPOSITE(UART5, UART5_MUX, UART5_DIV, UART5_GATE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1307)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1308) LPC32XX_DEFINE_MUX(UART6_MUX, UART6_CLK_CTRL, 16, 0x1, NULL, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1309) LPC32XX_DEFINE_CLK(UART6_DIV, UART6_CLK_CTRL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1310) 0, 0, 0, 0, 0, 0, lpc32xx_uart_div_ops),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1311) LPC32XX_DEFINE_GATE(UART6_GATE, UART_CLK_CTRL, 3, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1312) LPC32XX_DEFINE_COMPOSITE(UART6, UART6_MUX, UART6_DIV, UART6_GATE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1313)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1314) LPC32XX_DEFINE_CLK(IRDA, IRDA_CLK_CTRL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1315) 0, 0, 0, 0, 0, 0, lpc32xx_uart_div_ops),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1316)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1317) LPC32XX_DEFINE_MUX(TEST1_MUX, TEST_CLK_CTRL, 5, 0x3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1318) test1_mux_table, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1319) LPC32XX_DEFINE_GATE(TEST1_GATE, TEST_CLK_CTRL, 4, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1320) LPC32XX_DEFINE_COMPOSITE(TEST1, TEST1_MUX, _NULL, TEST1_GATE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1321)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1322) LPC32XX_DEFINE_MUX(TEST2_MUX, TEST_CLK_CTRL, 1, 0x7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1323) test2_mux_table, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1324) LPC32XX_DEFINE_GATE(TEST2_GATE, TEST_CLK_CTRL, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1325) LPC32XX_DEFINE_COMPOSITE(TEST2, TEST2_MUX, _NULL, TEST2_GATE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1326)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1327) LPC32XX_DEFINE_MUX(SYS, SYSCLK_CTRL, 0, 0x1, NULL, CLK_MUX_READ_ONLY),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1328)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1329) LPC32XX_DEFINE_DIV(USB_DIV_DIV, USB_DIV, 0, 4, NULL, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1330) LPC32XX_DEFINE_GATE(USB_DIV_GATE, USB_CTRL, 17, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1331) LPC32XX_DEFINE_COMPOSITE(USB_DIV, _NULL, USB_DIV_DIV, USB_DIV_GATE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1332)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1333) LPC32XX_DEFINE_DIV(SD_DIV, MS_CTRL, 0, 4, NULL, CLK_DIVIDER_ONE_BASED),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1334) LPC32XX_DEFINE_CLK(SD_GATE, MS_CTRL, BIT(5) | BIT(9), BIT(5) | BIT(9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1335) 0x0, BIT(5) | BIT(9), 0x0, 0x0, clk_mask_ops),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1336) LPC32XX_DEFINE_COMPOSITE(SD, _NULL, SD_DIV, SD_GATE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1337)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1338) LPC32XX_DEFINE_DIV(LCD_DIV, LCDCLK_CTRL, 0, 5, NULL, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1339) LPC32XX_DEFINE_GATE(LCD_GATE, LCDCLK_CTRL, 5, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1340) LPC32XX_DEFINE_COMPOSITE(LCD, _NULL, LCD_DIV, LCD_GATE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1341)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1342) LPC32XX_DEFINE_CLK(MAC, MACCLK_CTRL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1343) BIT(2) | BIT(1) | BIT(0), BIT(2) | BIT(1) | BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1344) BIT(2) | BIT(1) | BIT(0), BIT(2) | BIT(1) | BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1345) 0x0, 0x0, clk_mask_ops),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1346) LPC32XX_DEFINE_CLK(SLC, FLASHCLK_CTRL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1347) BIT(2) | BIT(0), BIT(2) | BIT(0), 0x0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1348) BIT(0), BIT(1), BIT(2) | BIT(1), clk_mask_ops),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1349) LPC32XX_DEFINE_CLK(MLC, FLASHCLK_CTRL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1350) BIT(1), BIT(2) | BIT(1), 0x0, BIT(1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1351) BIT(2) | BIT(0), BIT(2) | BIT(0), clk_mask_ops),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1352) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1353) * ADC/TS clock unfortunately cannot be registered as a composite one
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1354) * due to a different connection of gate, div and mux, e.g. gating it
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1355) * won't mean that the clock is off, if peripheral clock is its parent:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1356) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1357) * rtc-->[gate]-->| |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1358) * | mux |--> adc/ts
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1359) * pclk-->[div]-->| |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1360) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1361) * Constraints:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1362) * ADC --- resulting clock must be <= 4.5 MHz
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1363) * TS --- resulting clock must be <= 400 KHz
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1364) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1365) LPC32XX_DEFINE_DIV(ADC_DIV, ADCCLK_CTRL1, 0, 8, NULL, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1366) LPC32XX_DEFINE_GATE(ADC_RTC, ADCCLK_CTRL, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1367) LPC32XX_DEFINE_MUX(ADC, ADCCLK_CTRL1, 8, 0x1, NULL, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1368)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1369) /* USB controller clocks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1370) LPC32XX_DEFINE_USB(USB_AHB,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1371) BIT(24), 0x0, BIT(24), BIT(4), 0, clk_usb_ops),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1372) LPC32XX_DEFINE_USB(USB_OTG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1373) 0x0, 0x0, 0x0, BIT(3), 0, clk_usb_ops),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1374) LPC32XX_DEFINE_USB(USB_I2C,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1375) 0x0, BIT(23), BIT(23), BIT(2), 0, clk_usb_i2c_ops),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1376) LPC32XX_DEFINE_USB(USB_DEV,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1377) BIT(22), 0x0, BIT(22), BIT(1), BIT(0), clk_usb_ops),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1378) LPC32XX_DEFINE_USB(USB_HOST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1379) BIT(21), 0x0, BIT(21), BIT(0), BIT(1), clk_usb_ops),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1380) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1381)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1382) static struct clk * __init lpc32xx_clk_register(u32 id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1383) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1384) const struct clk_proto_t *lpc32xx_clk = &clk_proto[id];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1385) struct clk_hw_proto *clk_hw = &clk_hw_proto[id];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1386) const char *parents[LPC32XX_CLK_PARENTS_MAX];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1387) struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1388) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1389)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1390) for (i = 0; i < lpc32xx_clk->num_parents; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1391) parents[i] = clk_proto[lpc32xx_clk->parents[i]].name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1392)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1393) pr_debug("%s: derived from '%s', clock type %d\n", lpc32xx_clk->name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1394) parents[0], clk_hw->type);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1395)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1396) switch (clk_hw->type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1397) case CLK_LPC32XX:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1398) case CLK_LPC32XX_PLL:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1399) case CLK_LPC32XX_USB:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1400) case CLK_MUX:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1401) case CLK_DIV:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1402) case CLK_GATE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1403) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1404) struct clk_init_data clk_init = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1405) .name = lpc32xx_clk->name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1406) .parent_names = parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1407) .num_parents = lpc32xx_clk->num_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1408) .flags = lpc32xx_clk->flags,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1409) .ops = clk_hw->hw0.ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1410) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1411) struct clk_hw *hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1412)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1413) if (clk_hw->type == CLK_LPC32XX)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1414) hw = &clk_hw->hw0.clk.hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1415) else if (clk_hw->type == CLK_LPC32XX_PLL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1416) hw = &clk_hw->hw0.pll.hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1417) else if (clk_hw->type == CLK_LPC32XX_USB)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1418) hw = &clk_hw->hw0.usb_clk.hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1419) else if (clk_hw->type == CLK_MUX)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1420) hw = &clk_hw->hw0.mux.hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1421) else if (clk_hw->type == CLK_DIV)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1422) hw = &clk_hw->hw0.div.hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1423) else if (clk_hw->type == CLK_GATE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1424) hw = &clk_hw->hw0.gate.hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1425) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1426) return ERR_PTR(-EINVAL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1427)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1428) hw->init = &clk_init;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1429) clk = clk_register(NULL, hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1430) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1431) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1432) case CLK_COMPOSITE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1433) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1434) struct clk_hw *mux_hw = NULL, *div_hw = NULL, *gate_hw = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1435) const struct clk_ops *mops = NULL, *dops = NULL, *gops = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1436) struct clk_hw_proto0 *mux0, *div0, *gate0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1437)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1438) mux0 = clk_hw->hw1.mux;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1439) div0 = clk_hw->hw1.div;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1440) gate0 = clk_hw->hw1.gate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1441) if (mux0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1442) mops = mux0->ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1443) mux_hw = &mux0->clk.hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1444) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1445) if (div0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1446) dops = div0->ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1447) div_hw = &div0->clk.hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1448) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1449) if (gate0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1450) gops = gate0->ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1451) gate_hw = &gate0->clk.hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1452) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1453)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1454) clk = clk_register_composite(NULL, lpc32xx_clk->name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1455) parents, lpc32xx_clk->num_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1456) mux_hw, mops, div_hw, dops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1457) gate_hw, gops, lpc32xx_clk->flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1458) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1459) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1460) case CLK_FIXED:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1461) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1462) struct clk_fixed_rate *fixed = &clk_hw->f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1463)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1464) clk = clk_register_fixed_rate(NULL, lpc32xx_clk->name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1465) parents[0], 0, fixed->fixed_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1466) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1467) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1468) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1469) clk = ERR_PTR(-EINVAL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1470) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1471)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1472) return clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1473) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1474)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1475) static void __init lpc32xx_clk_div_quirk(u32 reg, u32 div_mask, u32 gate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1476) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1477) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1478)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1479) regmap_read(clk_regmap, reg, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1480)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1481) if (!(val & div_mask)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1482) val &= ~gate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1483) val |= BIT(__ffs(div_mask));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1484) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1485)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1486) regmap_update_bits(clk_regmap, reg, gate | div_mask, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1487) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1488)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1489) static void __init lpc32xx_clk_init(struct device_node *np)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1490) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1491) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1492) struct clk *clk_osc, *clk_32k;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1493) void __iomem *base = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1494)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1495) /* Ensure that parent clocks are available and valid */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1496) clk_32k = of_clk_get_by_name(np, clk_proto[LPC32XX_CLK_XTAL_32K].name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1497) if (IS_ERR(clk_32k)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1498) pr_err("failed to find external 32KHz clock: %ld\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1499) PTR_ERR(clk_32k));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1500) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1501) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1502) if (clk_get_rate(clk_32k) != 32768) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1503) pr_err("invalid clock rate of external 32KHz oscillator\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1504) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1505) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1506)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1507) clk_osc = of_clk_get_by_name(np, clk_proto[LPC32XX_CLK_XTAL].name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1508) if (IS_ERR(clk_osc)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1509) pr_err("failed to find external main oscillator clock: %ld\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1510) PTR_ERR(clk_osc));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1511) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1512) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1513)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1514) base = of_iomap(np, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1515) if (!base) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1516) pr_err("failed to map system control block registers\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1517) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1518) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1519)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1520) clk_regmap = regmap_init_mmio(NULL, base, &lpc32xx_scb_regmap_config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1521) if (IS_ERR(clk_regmap)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1522) pr_err("failed to regmap system control block: %ld\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1523) PTR_ERR(clk_regmap));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1524) iounmap(base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1525) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1526) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1527)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1528) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1529) * Divider part of PWM and MS clocks requires a quirk to avoid
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1530) * a misinterpretation of formally valid zero value in register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1531) * bitfield, which indicates another clock gate. Instead of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1532) * adding complexity to a gate clock ensure that zero value in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1533) * divider clock is never met in runtime.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1534) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1535) lpc32xx_clk_div_quirk(LPC32XX_CLKPWR_PWMCLK_CTRL, 0xf0, BIT(0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1536) lpc32xx_clk_div_quirk(LPC32XX_CLKPWR_PWMCLK_CTRL, 0xf00, BIT(2));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1537) lpc32xx_clk_div_quirk(LPC32XX_CLKPWR_MS_CTRL, 0xf, BIT(5) | BIT(9));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1538)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1539) for (i = 1; i < LPC32XX_CLK_MAX; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1540) clk[i] = lpc32xx_clk_register(i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1541) if (IS_ERR(clk[i])) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1542) pr_err("failed to register %s clock: %ld\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1543) clk_proto[i].name, PTR_ERR(clk[i]));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1544) clk[i] = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1545) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1546) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1547)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1548) of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1549)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1550) /* Set 48MHz rate of USB PLL clock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1551) clk_set_rate(clk[LPC32XX_CLK_USB_PLL], 48000000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1552)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1553) /* These two clocks must be always on independently on consumers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1554) clk_prepare_enable(clk[LPC32XX_CLK_ARM]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1555) clk_prepare_enable(clk[LPC32XX_CLK_HCLK]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1556)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1557) /* Enable ARM VFP by default */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1558) clk_prepare_enable(clk[LPC32XX_CLK_ARM_VFP]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1559)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1560) /* Disable enabled by default clocks for NAND MLC and SLC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1561) clk_mask_disable(&clk_hw_proto[LPC32XX_CLK_SLC].hw0.clk.hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1562) clk_mask_disable(&clk_hw_proto[LPC32XX_CLK_MLC].hw0.clk.hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1563) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1564) CLK_OF_DECLARE(lpc32xx_clk, "nxp,lpc3220-clk", lpc32xx_clk_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1565)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1566) static void __init lpc32xx_usb_clk_init(struct device_node *np)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1567) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1568) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1569)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1570) usb_clk_vbase = of_iomap(np, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1571) if (!usb_clk_vbase) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1572) pr_err("failed to map address range\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1573) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1574) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1575)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1576) for (i = 1; i < LPC32XX_USB_CLK_MAX; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1577) usb_clk[i] = lpc32xx_clk_register(i + LPC32XX_CLK_USB_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1578) if (IS_ERR(usb_clk[i])) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1579) pr_err("failed to register %s clock: %ld\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1580) clk_proto[i].name, PTR_ERR(usb_clk[i]));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1581) usb_clk[i] = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1582) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1583) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1584)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1585) of_clk_add_provider(np, of_clk_src_onecell_get, &usb_clk_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1586) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1587) CLK_OF_DECLARE(lpc32xx_usb_clk, "nxp,lpc3220-usb-clk", lpc32xx_usb_clk_init);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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