^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) * Clk driver for NXP LPC18xx/43xx Configuration Registers (CREG)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Copyright (C) 2015 Joachim Eastwood <manabian@gmail.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * This file is licensed under the terms of the GNU General Public
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * License version 2. This program is licensed "as is" without any
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * warranty of any kind, whether express or implied.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/clk-provider.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/mfd/syscon.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/regmap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define LPC18XX_CREG_CREG0 0x004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define LPC18XX_CREG_CREG0_EN1KHZ BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define LPC18XX_CREG_CREG0_EN32KHZ BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define LPC18XX_CREG_CREG0_RESET32KHZ BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define LPC18XX_CREG_CREG0_PD32KHZ BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define to_clk_creg(_hw) container_of(_hw, struct clk_creg_data, hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) CREG_CLK_1KHZ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) CREG_CLK_32KHZ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) CREG_CLK_MAX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) struct clk_creg_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) struct clk_hw hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) const char *name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) struct regmap *reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) unsigned int en_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) const struct clk_ops *ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define CREG_CLK(_name, _emask, _ops) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) .name = _name, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) .en_mask = LPC18XX_CREG_CREG0_##_emask, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) .ops = &_ops, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) static int clk_creg_32k_prepare(struct clk_hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) struct clk_creg_data *creg = to_clk_creg(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) ret = regmap_update_bits(creg->reg, LPC18XX_CREG_CREG0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) LPC18XX_CREG_CREG0_PD32KHZ |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) LPC18XX_CREG_CREG0_RESET32KHZ, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) * Powering up the 32k oscillator takes a long while
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) * and sadly there aren't any status bit to poll.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) msleep(2500);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) static void clk_creg_32k_unprepare(struct clk_hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) struct clk_creg_data *creg = to_clk_creg(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) regmap_update_bits(creg->reg, LPC18XX_CREG_CREG0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) LPC18XX_CREG_CREG0_PD32KHZ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) LPC18XX_CREG_CREG0_PD32KHZ);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) static int clk_creg_32k_is_prepared(struct clk_hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) struct clk_creg_data *creg = to_clk_creg(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) u32 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) regmap_read(creg->reg, LPC18XX_CREG_CREG0, ®);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) return !(reg & LPC18XX_CREG_CREG0_PD32KHZ) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) !(reg & LPC18XX_CREG_CREG0_RESET32KHZ);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) static unsigned long clk_creg_1k_recalc_rate(struct clk_hw *hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) unsigned long parent_rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) return parent_rate / 32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) static int clk_creg_enable(struct clk_hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) struct clk_creg_data *creg = to_clk_creg(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) return regmap_update_bits(creg->reg, LPC18XX_CREG_CREG0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) creg->en_mask, creg->en_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) static void clk_creg_disable(struct clk_hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) struct clk_creg_data *creg = to_clk_creg(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) regmap_update_bits(creg->reg, LPC18XX_CREG_CREG0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) creg->en_mask, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) static int clk_creg_is_enabled(struct clk_hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) struct clk_creg_data *creg = to_clk_creg(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) u32 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) regmap_read(creg->reg, LPC18XX_CREG_CREG0, ®);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) return !!(reg & creg->en_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) static const struct clk_ops clk_creg_32k = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) .enable = clk_creg_enable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) .disable = clk_creg_disable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) .is_enabled = clk_creg_is_enabled,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) .prepare = clk_creg_32k_prepare,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) .unprepare = clk_creg_32k_unprepare,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) .is_prepared = clk_creg_32k_is_prepared,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) static const struct clk_ops clk_creg_1k = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) .enable = clk_creg_enable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) .disable = clk_creg_disable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) .is_enabled = clk_creg_is_enabled,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) .recalc_rate = clk_creg_1k_recalc_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) static struct clk_creg_data clk_creg_clocks[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) [CREG_CLK_1KHZ] = CREG_CLK("1khz_clk", EN1KHZ, clk_creg_1k),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) [CREG_CLK_32KHZ] = CREG_CLK("32khz_clk", EN32KHZ, clk_creg_32k),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) static struct clk *clk_register_creg_clk(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) struct clk_creg_data *creg_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) const char **parent_name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) struct regmap *syscon)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) struct clk_init_data init;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) init.ops = creg_clk->ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) init.name = creg_clk->name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) init.parent_names = parent_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) init.num_parents = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) init.flags = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) creg_clk->reg = syscon;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) creg_clk->hw.init = &init;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) if (dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) return devm_clk_register(dev, &creg_clk->hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) return clk_register(NULL, &creg_clk->hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) static struct clk *clk_creg_early[CREG_CLK_MAX];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) static struct clk_onecell_data clk_creg_early_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) .clks = clk_creg_early,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) .clk_num = CREG_CLK_MAX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) static void __init lpc18xx_creg_clk_init(struct device_node *np)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) const char *clk_32khz_parent;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) struct regmap *syscon;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) syscon = syscon_node_to_regmap(np->parent);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) if (IS_ERR(syscon)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) pr_err("%s: syscon lookup failed\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) clk_32khz_parent = of_clk_get_parent_name(np, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) clk_creg_early[CREG_CLK_32KHZ] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) clk_register_creg_clk(NULL, &clk_creg_clocks[CREG_CLK_32KHZ],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) &clk_32khz_parent, syscon);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) clk_creg_early[CREG_CLK_1KHZ] = ERR_PTR(-EPROBE_DEFER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) of_clk_add_provider(np, of_clk_src_onecell_get, &clk_creg_early_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) CLK_OF_DECLARE_DRIVER(lpc18xx_creg_clk, "nxp,lpc1850-creg-clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) lpc18xx_creg_clk_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) static struct clk *clk_creg[CREG_CLK_MAX];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) static struct clk_onecell_data clk_creg_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) .clks = clk_creg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) .clk_num = CREG_CLK_MAX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) static int lpc18xx_creg_clk_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) struct device_node *np = pdev->dev.of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) struct regmap *syscon;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) syscon = syscon_node_to_regmap(np->parent);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) if (IS_ERR(syscon)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) dev_err(&pdev->dev, "syscon lookup failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) return PTR_ERR(syscon);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) clk_creg[CREG_CLK_32KHZ] = clk_creg_early[CREG_CLK_32KHZ];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) clk_creg[CREG_CLK_1KHZ] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) clk_register_creg_clk(NULL, &clk_creg_clocks[CREG_CLK_1KHZ],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) &clk_creg_clocks[CREG_CLK_32KHZ].name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) syscon);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) return of_clk_add_provider(np, of_clk_src_onecell_get, &clk_creg_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) static const struct of_device_id lpc18xx_creg_clk_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) { .compatible = "nxp,lpc1850-creg-clk" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) {},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) static struct platform_driver lpc18xx_creg_clk_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) .probe = lpc18xx_creg_clk_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) .name = "lpc18xx-creg-clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) .of_match_table = lpc18xx_creg_clk_of_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) builtin_platform_driver(lpc18xx_creg_clk_driver);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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