Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3)  * Copyright 2012 DENX Software Engineering, GmbH
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5)  * Pulled from code:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6)  * Portions copyright (C) 2003 Russell King, PXA MMCI Driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7)  * Portions copyright (C) 2004-2005 Pierre Ossman, W83L51xD SD/MMC driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9)  * Copyright 2008 Embedded Alley Solutions, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)  * Copyright 2009-2011 Freescale Semiconductor, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/spi/mxs-spi.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) void mxs_ssp_set_clk_rate(struct mxs_ssp *ssp, unsigned int rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) 	unsigned int ssp_clk, ssp_sck;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) 	u32 clock_divide, clock_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) 	u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) 	ssp_clk = clk_get_rate(ssp->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) 	for (clock_divide = 2; clock_divide <= 254; clock_divide += 2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) 		clock_rate = DIV_ROUND_UP(ssp_clk, rate * clock_divide);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) 		clock_rate = (clock_rate > 0) ? clock_rate - 1 : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) 		if (clock_rate <= 255)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) 			break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) 	if (clock_divide > 254) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) 		dev_err(ssp->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) 			"%s: cannot set clock to %d\n", __func__, rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) 		return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) 	ssp_sck = ssp_clk / clock_divide / (1 + clock_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) 	val = readl(ssp->base + HW_SSP_TIMING(ssp));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) 	val &= ~(BM_SSP_TIMING_CLOCK_DIVIDE | BM_SSP_TIMING_CLOCK_RATE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) 	val |= BF_SSP(clock_divide, TIMING_CLOCK_DIVIDE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) 	val |= BF_SSP(clock_rate, TIMING_CLOCK_RATE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) 	writel(val, ssp->base + HW_SSP_TIMING(ssp));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) 	ssp->clk_rate = ssp_sck;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) 	dev_dbg(ssp->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) 		"%s: clock_divide %d, clock_rate %d, ssp_clk %d, rate_actual %d, rate_requested %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) 		__func__, clock_divide, clock_rate, ssp_clk, ssp_sck, rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) EXPORT_SYMBOL_GPL(mxs_ssp_set_clk_rate);