Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * Copyright 2012 Freescale Semiconductor, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6) #include <linux/clk/mxs.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8) #include <linux/clk-provider.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #include <linux/of_address.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #include "clk.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) static void __iomem *clkctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) static void __iomem *digctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) #define CLKCTRL clkctrl
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) #define DIGCTRL digctrl
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) #define PLLCTRL0		(CLKCTRL + 0x0000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) #define CPU			(CLKCTRL + 0x0020)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) #define HBUS			(CLKCTRL + 0x0030)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) #define XBUS			(CLKCTRL + 0x0040)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) #define XTAL			(CLKCTRL + 0x0050)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) #define PIX			(CLKCTRL + 0x0060)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) #define SSP			(CLKCTRL + 0x0070)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) #define GPMI			(CLKCTRL + 0x0080)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) #define SPDIF			(CLKCTRL + 0x0090)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) #define EMI			(CLKCTRL + 0x00a0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) #define SAIF			(CLKCTRL + 0x00c0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) #define TV			(CLKCTRL + 0x00d0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) #define ETM			(CLKCTRL + 0x00e0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) #define FRAC			(CLKCTRL + 0x00f0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) #define CLKSEQ			(CLKCTRL + 0x0110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) #define BP_CPU_INTERRUPT_WAIT	12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) #define BP_CLKSEQ_BYPASS_SAIF	0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) #define BP_CLKSEQ_BYPASS_SSP	5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) #define BP_SAIF_DIV_FRAC_EN	16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) #define BP_FRAC_IOFRAC		24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) static void __init clk_misc_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) 	u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) 	/* Gate off cpu clock in WFI for power saving */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) 	writel_relaxed(1 << BP_CPU_INTERRUPT_WAIT, CPU + SET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) 	/* Clear BYPASS for SAIF */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) 	writel_relaxed(1 << BP_CLKSEQ_BYPASS_SAIF, CLKSEQ + CLR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) 	/* SAIF has to use frac div for functional operation */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) 	val = readl_relaxed(SAIF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) 	val |= 1 << BP_SAIF_DIV_FRAC_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) 	writel_relaxed(val, SAIF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) 	 * Source ssp clock from ref_io than ref_xtal,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 	 * as ref_xtal only provides 24 MHz as maximum.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 	writel_relaxed(1 << BP_CLKSEQ_BYPASS_SSP, CLKSEQ + CLR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 	 * 480 MHz seems too high to be ssp clock source directly,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) 	 * so set frac to get a 288 MHz ref_io.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 	writel_relaxed(0x3f << BP_FRAC_IOFRAC, FRAC + CLR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 	writel_relaxed(30 << BP_FRAC_IOFRAC, FRAC + SET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) static const char *const sel_pll[]  __initconst = { "pll", "ref_xtal", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) static const char *const sel_cpu[]  __initconst = { "ref_cpu", "ref_xtal", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) static const char *const sel_pix[]  __initconst = { "ref_pix", "ref_xtal", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) static const char *const sel_io[]   __initconst = { "ref_io", "ref_xtal", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) static const char *const cpu_sels[] __initconst = { "cpu_pll", "cpu_xtal", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) static const char *const emi_sels[] __initconst = { "emi_pll", "emi_xtal", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) enum imx23_clk {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 	ref_xtal, pll, ref_cpu, ref_emi, ref_pix, ref_io, saif_sel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 	lcdif_sel, gpmi_sel, ssp_sel, emi_sel, cpu, etm_sel, cpu_pll,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 	cpu_xtal, hbus, xbus, lcdif_div, ssp_div, gpmi_div, emi_pll,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 	emi_xtal, etm_div, saif_div, clk32k_div, rtc, adc, spdif_div,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 	clk32k, dri, pwm, filt, uart, ssp, gpmi, spdif, emi, saif,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 	lcdif, etm, usb, usb_phy,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 	clk_max
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) static struct clk *clks[clk_max];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) static struct clk_onecell_data clk_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) static enum imx23_clk clks_init_on[] __initdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 	cpu, hbus, xbus, emi, uart,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) static void __init mx23_clocks_init(struct device_node *np)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 	struct device_node *dcnp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 	u32 i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 	dcnp = of_find_compatible_node(NULL, NULL, "fsl,imx23-digctl");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 	digctrl = of_iomap(dcnp, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 	WARN_ON(!digctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 	of_node_put(dcnp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 	clkctrl = of_iomap(np, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 	WARN_ON(!clkctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 	clk_misc_init();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 	clks[ref_xtal] = mxs_clk_fixed("ref_xtal", 24000000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 	clks[pll] = mxs_clk_pll("pll", "ref_xtal", PLLCTRL0, 16, 480000000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 	clks[ref_cpu] = mxs_clk_ref("ref_cpu", "pll", FRAC, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 	clks[ref_emi] = mxs_clk_ref("ref_emi", "pll", FRAC, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 	clks[ref_pix] = mxs_clk_ref("ref_pix", "pll", FRAC, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 	clks[ref_io] = mxs_clk_ref("ref_io", "pll", FRAC, 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 	clks[saif_sel] = mxs_clk_mux("saif_sel", CLKSEQ, 0, 1, sel_pll, ARRAY_SIZE(sel_pll));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 	clks[lcdif_sel] = mxs_clk_mux("lcdif_sel", CLKSEQ, 1, 1, sel_pix, ARRAY_SIZE(sel_pix));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 	clks[gpmi_sel] = mxs_clk_mux("gpmi_sel", CLKSEQ, 4, 1, sel_io, ARRAY_SIZE(sel_io));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 	clks[ssp_sel] = mxs_clk_mux("ssp_sel", CLKSEQ, 5, 1, sel_io, ARRAY_SIZE(sel_io));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 	clks[emi_sel] = mxs_clk_mux("emi_sel", CLKSEQ, 6, 1, emi_sels, ARRAY_SIZE(emi_sels));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 	clks[cpu] = mxs_clk_mux("cpu", CLKSEQ, 7, 1, cpu_sels, ARRAY_SIZE(cpu_sels));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 	clks[etm_sel] = mxs_clk_mux("etm_sel", CLKSEQ, 8, 1, sel_cpu, ARRAY_SIZE(sel_cpu));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 	clks[cpu_pll] = mxs_clk_div("cpu_pll", "ref_cpu", CPU, 0, 6, 28);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 	clks[cpu_xtal] = mxs_clk_div("cpu_xtal", "ref_xtal", CPU, 16, 10, 29);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 	clks[hbus] = mxs_clk_div("hbus", "cpu", HBUS, 0, 5, 29);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 	clks[xbus] = mxs_clk_div("xbus", "ref_xtal", XBUS, 0, 10, 31);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 	clks[lcdif_div] = mxs_clk_div("lcdif_div", "lcdif_sel", PIX, 0, 12, 29);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 	clks[ssp_div] = mxs_clk_div("ssp_div", "ssp_sel", SSP, 0, 9, 29);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 	clks[gpmi_div] = mxs_clk_div("gpmi_div", "gpmi_sel", GPMI, 0, 10, 29);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 	clks[emi_pll] = mxs_clk_div("emi_pll", "ref_emi", EMI, 0, 6, 28);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 	clks[emi_xtal] = mxs_clk_div("emi_xtal", "ref_xtal", EMI, 8, 4, 29);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 	clks[etm_div] = mxs_clk_div("etm_div", "etm_sel", ETM, 0, 6, 29);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 	clks[saif_div] = mxs_clk_frac("saif_div", "saif_sel", SAIF, 0, 16, 29);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 	clks[clk32k_div] = mxs_clk_fixed_factor("clk32k_div", "ref_xtal", 1, 750);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 	clks[rtc] = mxs_clk_fixed_factor("rtc", "ref_xtal", 1, 768);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 	clks[adc] = mxs_clk_fixed_factor("adc", "clk32k", 1, 16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 	clks[spdif_div] = mxs_clk_fixed_factor("spdif_div", "pll", 1, 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 	clks[clk32k] = mxs_clk_gate("clk32k", "clk32k_div", XTAL, 26);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 	clks[dri] = mxs_clk_gate("dri", "ref_xtal", XTAL, 28);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 	clks[pwm] = mxs_clk_gate("pwm", "ref_xtal", XTAL, 29);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 	clks[filt] = mxs_clk_gate("filt", "ref_xtal", XTAL, 30);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 	clks[uart] = mxs_clk_gate("uart", "ref_xtal", XTAL, 31);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 	clks[ssp] = mxs_clk_gate("ssp", "ssp_div", SSP, 31);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 	clks[gpmi] = mxs_clk_gate("gpmi", "gpmi_div", GPMI, 31);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 	clks[spdif] = mxs_clk_gate("spdif", "spdif_div", SPDIF, 31);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 	clks[emi] = mxs_clk_gate("emi", "emi_sel", EMI, 31);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 	clks[saif] = mxs_clk_gate("saif", "saif_div", SAIF, 31);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 	clks[lcdif] = mxs_clk_gate("lcdif", "lcdif_div", PIX, 31);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 	clks[etm] = mxs_clk_gate("etm", "etm_div", ETM, 31);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 	clks[usb] = mxs_clk_gate("usb", "usb_phy", DIGCTRL, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 	clks[usb_phy] = clk_register_gate(NULL, "usb_phy", "pll", 0, PLLCTRL0, 18, 0, &mxs_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 	for (i = 0; i < ARRAY_SIZE(clks); i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 		if (IS_ERR(clks[i])) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 			pr_err("i.MX23 clk %d: register failed with %ld\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 				i, PTR_ERR(clks[i]));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 			return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 	clk_data.clks = clks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 	clk_data.clk_num = ARRAY_SIZE(clks);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 	of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 	for (i = 0; i < ARRAY_SIZE(clks_init_on); i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 		clk_prepare_enable(clks[clks_init_on[i]]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) CLK_OF_DECLARE(imx23_clkctrl, "fsl,imx23-clkctrl", mx23_clocks_init);