^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Marvell MV98DX3236 SoC clocks
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2012 Marvell
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Gregory CLEMENT <gregory.clement@free-electrons.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * Andrew Lunn <andrew@lunn.ch>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/clk-provider.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include "common.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) * For 98DX4251 Sample At Reset the CPU, DDR and Main PLL clocks are all
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) * defined at the same time
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) * SAR1[20:18] : CPU frequency DDR frequency MPLL frequency
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) * 0 = 400 MHz 400 MHz 800 MHz
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) * 2 = 667 MHz 667 MHz 2000 MHz
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) * 3 = 800 MHz 800 MHz 1600 MHz
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) * others reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) * For 98DX3236 Sample At Reset the CPU, DDR and Main PLL clocks are all
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) * defined at the same time
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) * SAR1[20:18] : CPU frequency DDR frequency MPLL frequency
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) * 1 = 667 MHz 667 MHz 2000 MHz
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) * 2 = 400 MHz 400 MHz 400 MHz
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) * 3 = 800 MHz 800 MHz 800 MHz
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) * 5 = 800 MHz 400 MHz 800 MHz
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) * others reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define SAR1_MV98DX3236_CPU_DDR_MPLL_FREQ_OPT 18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define SAR1_MV98DX3236_CPU_DDR_MPLL_FREQ_OPT_MASK 0x7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) static u32 __init mv98dx3236_get_tclk_freq(void __iomem *sar)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) /* Tclk = 200MHz, no SaR dependency */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) return 200000000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) static const u32 mv98dx3236_cpu_frequencies[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) 667000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) 400000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) 800000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) 800000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) static const u32 mv98dx4251_cpu_frequencies[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) 400000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) 667000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) 800000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) 0, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) static u32 __init mv98dx3236_get_cpu_freq(void __iomem *sar)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) u32 cpu_freq = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) u8 cpu_freq_select = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) cpu_freq_select = ((readl(sar) >> SAR1_MV98DX3236_CPU_DDR_MPLL_FREQ_OPT) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) SAR1_MV98DX3236_CPU_DDR_MPLL_FREQ_OPT_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) if (of_machine_is_compatible("marvell,armadaxp-98dx4251"))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) cpu_freq = mv98dx4251_cpu_frequencies[cpu_freq_select];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) else if (of_machine_is_compatible("marvell,armadaxp-98dx3236"))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) cpu_freq = mv98dx3236_cpu_frequencies[cpu_freq_select];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) if (!cpu_freq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) pr_err("CPU freq select unsupported %d\n", cpu_freq_select);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) return cpu_freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) MV98DX3236_CPU_TO_DDR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) MV98DX3236_CPU_TO_MPLL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) static const struct coreclk_ratio mv98dx3236_core_ratios[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) { .id = MV98DX3236_CPU_TO_DDR, .name = "ddrclk" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) { .id = MV98DX3236_CPU_TO_MPLL, .name = "mpll" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) static const int __initconst mv98dx3236_cpu_mpll_ratios[8][2] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) {0, 1}, {3, 1}, {1, 1}, {1, 1},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) {0, 1}, {1, 1}, {0, 1}, {0, 1},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) static const int __initconst mv98dx3236_cpu_ddr_ratios[8][2] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) {0, 1}, {1, 1}, {1, 1}, {1, 1},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) {0, 1}, {1, 2}, {0, 1}, {0, 1},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) static const int __initconst mv98dx4251_cpu_mpll_ratios[8][2] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) {2, 1}, {0, 1}, {3, 1}, {2, 1},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) {0, 1}, {0, 1}, {0, 1}, {0, 1},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) static const int __initconst mv98dx4251_cpu_ddr_ratios[8][2] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) {1, 1}, {0, 1}, {1, 1}, {1, 1},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) {0, 1}, {0, 1}, {0, 1}, {0, 1},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) static void __init mv98dx3236_get_clk_ratio(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) void __iomem *sar, int id, int *mult, int *div)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) u32 opt = ((readl(sar) >> SAR1_MV98DX3236_CPU_DDR_MPLL_FREQ_OPT) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) SAR1_MV98DX3236_CPU_DDR_MPLL_FREQ_OPT_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) switch (id) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) case MV98DX3236_CPU_TO_DDR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) if (of_machine_is_compatible("marvell,armadaxp-98dx4251")) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) *mult = mv98dx4251_cpu_ddr_ratios[opt][0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) *div = mv98dx4251_cpu_ddr_ratios[opt][1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) } else if (of_machine_is_compatible("marvell,armadaxp-98dx3236")) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) *mult = mv98dx3236_cpu_ddr_ratios[opt][0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) *div = mv98dx3236_cpu_ddr_ratios[opt][1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) case MV98DX3236_CPU_TO_MPLL:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) if (of_machine_is_compatible("marvell,armadaxp-98dx4251")) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) *mult = mv98dx4251_cpu_mpll_ratios[opt][0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) *div = mv98dx4251_cpu_mpll_ratios[opt][1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) } else if (of_machine_is_compatible("marvell,armadaxp-98dx3236")) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) *mult = mv98dx3236_cpu_mpll_ratios[opt][0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) *div = mv98dx3236_cpu_mpll_ratios[opt][1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) static const struct coreclk_soc_desc mv98dx3236_core_clocks = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) .get_tclk_freq = mv98dx3236_get_tclk_freq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) .get_cpu_freq = mv98dx3236_get_cpu_freq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) .get_clk_ratio = mv98dx3236_get_clk_ratio,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) .ratios = mv98dx3236_core_ratios,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) .num_ratios = ARRAY_SIZE(mv98dx3236_core_ratios),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) * Clock Gating Control
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) static const struct clk_gating_soc_desc mv98dx3236_gating_desc[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) { "ge1", NULL, 3, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) { "ge0", NULL, 4, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) { "pex00", NULL, 5, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) { "sdio", NULL, 17, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) { "usb0", NULL, 18, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) { "xor0", NULL, 22, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) static void __init mv98dx3236_clk_init(struct device_node *np)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) struct device_node *cgnp =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) of_find_compatible_node(NULL, NULL, "marvell,mv98dx3236-gating-clock");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) mvebu_coreclk_setup(np, &mv98dx3236_core_clocks);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) if (cgnp) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) mvebu_clk_gating_setup(cgnp, mv98dx3236_gating_desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) of_node_put(cgnp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) CLK_OF_DECLARE(mv98dx3236_clk, "marvell,mv98dx3236-core-clock", mv98dx3236_clk_init);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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