^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Marvell Kirkwood SoC clocks
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2012 Marvell
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Gregory CLEMENT <gregory.clement@free-electrons.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * Andrew Lunn <andrew@lunn.ch>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/clk-provider.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/of_address.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include "common.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) * Core Clocks
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) * Kirkwood PLL sample-at-reset configuration
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) * (6180 has different SAR layout than other Kirkwood SoCs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) * SAR0[4:3,22,1] : CPU frequency (6281,6292,6282)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) * 4 = 600 MHz
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) * 6 = 800 MHz
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) * 7 = 1000 MHz
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) * 9 = 1200 MHz
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) * 12 = 1500 MHz
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) * 13 = 1600 MHz
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) * 14 = 1800 MHz
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) * 15 = 2000 MHz
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) * others reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) * SAR0[19,10:9] : CPU to L2 Clock divider ratio (6281,6292,6282)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) * 1 = (1/2) * CPU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) * 3 = (1/3) * CPU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) * 5 = (1/4) * CPU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) * others reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) * SAR0[8:5] : CPU to DDR DRAM Clock divider ratio (6281,6292,6282)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) * 2 = (1/2) * CPU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) * 4 = (1/3) * CPU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) * 6 = (1/4) * CPU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) * 7 = (2/9) * CPU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) * 8 = (1/5) * CPU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) * 9 = (1/6) * CPU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) * others reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) * SAR0[4:2] : Kirkwood 6180 cpu/l2/ddr clock configuration (6180 only)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) * 5 = [CPU = 600 MHz, L2 = (1/2) * CPU, DDR = 200 MHz = (1/3) * CPU]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) * 6 = [CPU = 800 MHz, L2 = (1/2) * CPU, DDR = 200 MHz = (1/4) * CPU]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) * 7 = [CPU = 1000 MHz, L2 = (1/2) * CPU, DDR = 200 MHz = (1/5) * CPU]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) * others reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) * SAR0[21] : TCLK frequency
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) * 0 = 200 MHz
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) * 1 = 166 MHz
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) * others reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define SAR_KIRKWOOD_CPU_FREQ(x) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) (((x & (1 << 1)) >> 1) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) ((x & (1 << 22)) >> 21) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) ((x & (3 << 3)) >> 1))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define SAR_KIRKWOOD_L2_RATIO(x) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) (((x & (3 << 9)) >> 9) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) (((x & (1 << 19)) >> 17)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define SAR_KIRKWOOD_DDR_RATIO 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define SAR_KIRKWOOD_DDR_RATIO_MASK 0xf
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define SAR_MV88F6180_CLK 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define SAR_MV88F6180_CLK_MASK 0x7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define SAR_KIRKWOOD_TCLK_FREQ 21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define SAR_KIRKWOOD_TCLK_FREQ_MASK 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) enum { KIRKWOOD_CPU_TO_L2, KIRKWOOD_CPU_TO_DDR };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) static const struct coreclk_ratio kirkwood_coreclk_ratios[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) { .id = KIRKWOOD_CPU_TO_L2, .name = "l2clk", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) { .id = KIRKWOOD_CPU_TO_DDR, .name = "ddrclk", }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) static u32 __init kirkwood_get_tclk_freq(void __iomem *sar)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) u32 opt = (readl(sar) >> SAR_KIRKWOOD_TCLK_FREQ) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) SAR_KIRKWOOD_TCLK_FREQ_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) return (opt) ? 166666667 : 200000000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) static const u32 kirkwood_cpu_freqs[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) 0, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) 600000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) 800000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) 1000000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 1200000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 1500000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 1600000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 1800000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 2000000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) static u32 __init kirkwood_get_cpu_freq(void __iomem *sar)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) u32 opt = SAR_KIRKWOOD_CPU_FREQ(readl(sar));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) return kirkwood_cpu_freqs[opt];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) static const int kirkwood_cpu_l2_ratios[8][2] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) { 0, 1 }, { 1, 2 }, { 0, 1 }, { 1, 3 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) { 0, 1 }, { 1, 4 }, { 0, 1 }, { 0, 1 }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) static const int kirkwood_cpu_ddr_ratios[16][2] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) { 0, 1 }, { 0, 1 }, { 1, 2 }, { 0, 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) { 1, 3 }, { 0, 1 }, { 1, 4 }, { 2, 9 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) { 1, 5 }, { 1, 6 }, { 0, 1 }, { 0, 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) { 0, 1 }, { 0, 1 }, { 0, 1 }, { 0, 1 }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) static void __init kirkwood_get_clk_ratio(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) void __iomem *sar, int id, int *mult, int *div)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) switch (id) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) case KIRKWOOD_CPU_TO_L2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) u32 opt = SAR_KIRKWOOD_L2_RATIO(readl(sar));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) *mult = kirkwood_cpu_l2_ratios[opt][0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) *div = kirkwood_cpu_l2_ratios[opt][1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) case KIRKWOOD_CPU_TO_DDR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) u32 opt = (readl(sar) >> SAR_KIRKWOOD_DDR_RATIO) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) SAR_KIRKWOOD_DDR_RATIO_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) *mult = kirkwood_cpu_ddr_ratios[opt][0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) *div = kirkwood_cpu_ddr_ratios[opt][1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) static const u32 mv88f6180_cpu_freqs[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 0, 0, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 600000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 800000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 1000000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) static u32 __init mv88f6180_get_cpu_freq(void __iomem *sar)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) u32 opt = (readl(sar) >> SAR_MV88F6180_CLK) & SAR_MV88F6180_CLK_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) return mv88f6180_cpu_freqs[opt];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) static const int mv88f6180_cpu_ddr_ratios[8][2] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) { 0, 1 }, { 0, 1 }, { 0, 1 }, { 0, 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) { 0, 1 }, { 1, 3 }, { 1, 4 }, { 1, 5 }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) static void __init mv88f6180_get_clk_ratio(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) void __iomem *sar, int id, int *mult, int *div)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) switch (id) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) case KIRKWOOD_CPU_TO_L2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) /* mv88f6180 has a fixed 1:2 CPU-to-L2 ratio */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) *mult = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) *div = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) case KIRKWOOD_CPU_TO_DDR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) u32 opt = (readl(sar) >> SAR_MV88F6180_CLK) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) SAR_MV88F6180_CLK_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) *mult = mv88f6180_cpu_ddr_ratios[opt][0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) *div = mv88f6180_cpu_ddr_ratios[opt][1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) static u32 __init mv98dx1135_get_tclk_freq(void __iomem *sar)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) return 166666667;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) static const struct coreclk_soc_desc kirkwood_coreclks = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) .get_tclk_freq = kirkwood_get_tclk_freq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) .get_cpu_freq = kirkwood_get_cpu_freq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) .get_clk_ratio = kirkwood_get_clk_ratio,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) .ratios = kirkwood_coreclk_ratios,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) .num_ratios = ARRAY_SIZE(kirkwood_coreclk_ratios),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) static const struct coreclk_soc_desc mv88f6180_coreclks = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) .get_tclk_freq = kirkwood_get_tclk_freq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) .get_cpu_freq = mv88f6180_get_cpu_freq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) .get_clk_ratio = mv88f6180_get_clk_ratio,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) .ratios = kirkwood_coreclk_ratios,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) .num_ratios = ARRAY_SIZE(kirkwood_coreclk_ratios),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) static const struct coreclk_soc_desc mv98dx1135_coreclks = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) .get_tclk_freq = mv98dx1135_get_tclk_freq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) .get_cpu_freq = kirkwood_get_cpu_freq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) .get_clk_ratio = kirkwood_get_clk_ratio,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) .ratios = kirkwood_coreclk_ratios,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) .num_ratios = ARRAY_SIZE(kirkwood_coreclk_ratios),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) * Clock Gating Control
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) static const struct clk_gating_soc_desc kirkwood_gating_desc[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) { "ge0", NULL, 0, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) { "pex0", NULL, 2, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) { "usb0", NULL, 3, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) { "sdio", NULL, 4, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) { "tsu", NULL, 5, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) { "runit", NULL, 7, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) { "xor0", NULL, 8, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) { "audio", NULL, 9, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) { "sata0", NULL, 14, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) { "sata1", NULL, 15, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) { "xor1", NULL, 16, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) { "crypto", NULL, 17, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) { "pex1", NULL, 18, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) { "ge1", NULL, 19, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) { "tdm", NULL, 20, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) * Clock Muxing Control
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) struct clk_muxing_soc_desc {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) const char *name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) const char **parents;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) int num_parents;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) int shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) int width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) struct clk_muxing_ctrl {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) spinlock_t *lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) struct clk **muxes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) int num_muxes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) static const char *powersave_parents[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) "cpuclk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) "ddrclk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) static const struct clk_muxing_soc_desc kirkwood_mux_desc[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) { "powersave", powersave_parents, ARRAY_SIZE(powersave_parents),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) 11, 1, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) static struct clk *clk_muxing_get_src(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) struct of_phandle_args *clkspec, void *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) struct clk_muxing_ctrl *ctrl = (struct clk_muxing_ctrl *)data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) int n;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) if (clkspec->args_count < 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) return ERR_PTR(-EINVAL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) for (n = 0; n < ctrl->num_muxes; n++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) struct clk_mux *mux =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) to_clk_mux(__clk_get_hw(ctrl->muxes[n]));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) if (clkspec->args[0] == mux->shift)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) return ctrl->muxes[n];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) return ERR_PTR(-ENODEV);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) static void __init kirkwood_clk_muxing_setup(struct device_node *np,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) const struct clk_muxing_soc_desc *desc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) struct clk_muxing_ctrl *ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) int n;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) base = of_iomap(np, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) if (WARN_ON(!base))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) ctrl = kzalloc(sizeof(*ctrl), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) if (WARN_ON(!ctrl))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) goto ctrl_out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) /* lock must already be initialized */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) ctrl->lock = &ctrl_gating_lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) /* Count, allocate, and register clock muxes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) for (n = 0; desc[n].name;)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) n++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) ctrl->num_muxes = n;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) ctrl->muxes = kcalloc(ctrl->num_muxes, sizeof(struct clk *),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) if (WARN_ON(!ctrl->muxes))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) goto muxes_out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) for (n = 0; n < ctrl->num_muxes; n++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) ctrl->muxes[n] = clk_register_mux(NULL, desc[n].name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) desc[n].parents, desc[n].num_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) desc[n].flags, base, desc[n].shift,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) desc[n].width, desc[n].flags, ctrl->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) WARN_ON(IS_ERR(ctrl->muxes[n]));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) of_clk_add_provider(np, clk_muxing_get_src, ctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) muxes_out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) kfree(ctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) ctrl_out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) iounmap(base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) static void __init kirkwood_clk_init(struct device_node *np)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) struct device_node *cgnp =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) of_find_compatible_node(NULL, NULL, "marvell,kirkwood-gating-clock");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) if (of_device_is_compatible(np, "marvell,mv88f6180-core-clock"))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) mvebu_coreclk_setup(np, &mv88f6180_coreclks);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) else if (of_device_is_compatible(np, "marvell,mv98dx1135-core-clock"))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) mvebu_coreclk_setup(np, &mv98dx1135_coreclks);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) mvebu_coreclk_setup(np, &kirkwood_coreclks);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) if (cgnp) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) mvebu_clk_gating_setup(cgnp, kirkwood_gating_desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) kirkwood_clk_muxing_setup(cgnp, kirkwood_mux_desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) of_node_put(cgnp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) CLK_OF_DECLARE(kirkwood_clk, "marvell,kirkwood-core-clock",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) kirkwood_clk_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) CLK_OF_DECLARE(mv88f6180_clk, "marvell,mv88f6180-core-clock",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) kirkwood_clk_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) CLK_OF_DECLARE(98dx1135_clk, "marvell,mv98dx1135-core-clock",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) kirkwood_clk_init);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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