^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Marvell Dove SoC clocks
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2012 Marvell
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Gregory CLEMENT <gregory.clement@free-electrons.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * Andrew Lunn <andrew@lunn.ch>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/clk-provider.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include "common.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include "dove-divider.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) * Core Clocks
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) * Dove PLL sample-at-reset configuration
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) * SAR0[8:5] : CPU frequency
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) * 5 = 1000 MHz
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) * 6 = 933 MHz
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) * 7 = 933 MHz
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) * 8 = 800 MHz
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) * 9 = 800 MHz
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) * 10 = 800 MHz
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) * 11 = 1067 MHz
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) * 12 = 667 MHz
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) * 13 = 533 MHz
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) * 14 = 400 MHz
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) * 15 = 333 MHz
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) * others reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) * SAR0[11:9] : CPU to L2 Clock divider ratio
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) * 0 = (1/1) * CPU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) * 2 = (1/2) * CPU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) * 4 = (1/3) * CPU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) * 6 = (1/4) * CPU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) * others reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) * SAR0[15:12] : CPU to DDR DRAM Clock divider ratio
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) * 0 = (1/1) * CPU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) * 2 = (1/2) * CPU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) * 3 = (2/5) * CPU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) * 4 = (1/3) * CPU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) * 6 = (1/4) * CPU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) * 8 = (1/5) * CPU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) * 10 = (1/6) * CPU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) * 12 = (1/7) * CPU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) * 14 = (1/8) * CPU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) * 15 = (1/10) * CPU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) * others reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) * SAR0[24:23] : TCLK frequency
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) * 0 = 166 MHz
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) * 1 = 125 MHz
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) * others reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define SAR_DOVE_CPU_FREQ 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define SAR_DOVE_CPU_FREQ_MASK 0xf
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define SAR_DOVE_L2_RATIO 9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define SAR_DOVE_L2_RATIO_MASK 0x7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define SAR_DOVE_DDR_RATIO 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define SAR_DOVE_DDR_RATIO_MASK 0xf
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define SAR_DOVE_TCLK_FREQ 23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define SAR_DOVE_TCLK_FREQ_MASK 0x3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) enum { DOVE_CPU_TO_L2, DOVE_CPU_TO_DDR };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) static const struct coreclk_ratio dove_coreclk_ratios[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) { .id = DOVE_CPU_TO_L2, .name = "l2clk", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) { .id = DOVE_CPU_TO_DDR, .name = "ddrclk", }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) static const u32 dove_tclk_freqs[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) 166666667,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) 125000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) 0, 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) static u32 __init dove_get_tclk_freq(void __iomem *sar)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) u32 opt = (readl(sar) >> SAR_DOVE_TCLK_FREQ) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) SAR_DOVE_TCLK_FREQ_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) return dove_tclk_freqs[opt];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) static const u32 dove_cpu_freqs[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) 0, 0, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) 1000000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) 933333333, 933333333,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) 800000000, 800000000, 800000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) 1066666667,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 666666667,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 533333333,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 400000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 333333333
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) static u32 __init dove_get_cpu_freq(void __iomem *sar)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) u32 opt = (readl(sar) >> SAR_DOVE_CPU_FREQ) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) SAR_DOVE_CPU_FREQ_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) return dove_cpu_freqs[opt];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) static const int dove_cpu_l2_ratios[8][2] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) { 1, 1 }, { 0, 1 }, { 1, 2 }, { 0, 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) { 1, 3 }, { 0, 1 }, { 1, 4 }, { 0, 1 }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) static const int dove_cpu_ddr_ratios[16][2] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) { 1, 1 }, { 0, 1 }, { 1, 2 }, { 2, 5 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) { 1, 3 }, { 0, 1 }, { 1, 4 }, { 0, 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) { 1, 5 }, { 0, 1 }, { 1, 6 }, { 0, 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) { 1, 7 }, { 0, 1 }, { 1, 8 }, { 1, 10 }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) static void __init dove_get_clk_ratio(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) void __iomem *sar, int id, int *mult, int *div)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) switch (id) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) case DOVE_CPU_TO_L2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) u32 opt = (readl(sar) >> SAR_DOVE_L2_RATIO) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) SAR_DOVE_L2_RATIO_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) *mult = dove_cpu_l2_ratios[opt][0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) *div = dove_cpu_l2_ratios[opt][1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) case DOVE_CPU_TO_DDR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) u32 opt = (readl(sar) >> SAR_DOVE_DDR_RATIO) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) SAR_DOVE_DDR_RATIO_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) *mult = dove_cpu_ddr_ratios[opt][0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) *div = dove_cpu_ddr_ratios[opt][1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) static const struct coreclk_soc_desc dove_coreclks = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) .get_tclk_freq = dove_get_tclk_freq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) .get_cpu_freq = dove_get_cpu_freq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) .get_clk_ratio = dove_get_clk_ratio,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) .ratios = dove_coreclk_ratios,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) .num_ratios = ARRAY_SIZE(dove_coreclk_ratios),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) * Clock Gating Control
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) static const struct clk_gating_soc_desc dove_gating_desc[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) { "usb0", NULL, 0, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) { "usb1", NULL, 1, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) { "ge", "gephy", 2, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) { "sata", NULL, 3, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) { "pex0", NULL, 4, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) { "pex1", NULL, 5, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) { "sdio0", NULL, 8, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) { "sdio1", NULL, 9, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) { "nand", NULL, 10, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) { "camera", NULL, 11, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) { "i2s0", NULL, 12, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) { "i2s1", NULL, 13, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) { "crypto", NULL, 15, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) { "ac97", NULL, 21, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) { "pdma", NULL, 22, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) { "xor0", NULL, 23, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) { "xor1", NULL, 24, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) { "gephy", NULL, 30, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) static void __init dove_clk_init(struct device_node *np)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) struct device_node *cgnp =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) of_find_compatible_node(NULL, NULL, "marvell,dove-gating-clock");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) struct device_node *ddnp =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) of_find_compatible_node(NULL, NULL, "marvell,dove-divider-clock");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) mvebu_coreclk_setup(np, &dove_coreclks);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) if (ddnp) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) dove_divider_clk_init(ddnp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) of_node_put(ddnp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) if (cgnp) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) mvebu_clk_gating_setup(cgnp, dove_gating_desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) of_node_put(cgnp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) CLK_OF_DECLARE(dove_clk, "marvell,dove-core-clock", dove_clk_init);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
3 Commits
0 Branches
0 Tags