Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * Marvell Dove PMU Core PLL divider driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  * Cleaned up by substantially rewriting, and converted to DT by
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  * Russell King.  Origin is not known.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8) #include <linux/clk-provider.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #include <linux/of_address.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #include "dove-divider.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) struct dove_clk {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) 	const char *name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) 	struct clk_hw hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) 	void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) 	spinlock_t *lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) 	u8 div_bit_start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) 	u8 div_bit_end;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) 	u8 div_bit_load;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) 	u8 div_bit_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) 	u32 *divider_table;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) 	DIV_CTRL0 = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) 	DIV_CTRL1 = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) 	DIV_CTRL1_N_RESET_MASK = BIT(10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) #define to_dove_clk(hw) container_of(hw, struct dove_clk, hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) static void dove_load_divider(void __iomem *base, u32 val, u32 mask, u32 load)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) 	u32 v;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) 	v = readl_relaxed(base + DIV_CTRL1) | DIV_CTRL1_N_RESET_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) 	writel_relaxed(v, base + DIV_CTRL1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) 	v = (readl_relaxed(base + DIV_CTRL0) & ~(mask | load)) | val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) 	writel_relaxed(v, base + DIV_CTRL0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) 	writel_relaxed(v | load, base + DIV_CTRL0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) 	ndelay(250);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) 	writel_relaxed(v, base + DIV_CTRL0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) static unsigned int dove_get_divider(struct dove_clk *dc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) 	unsigned int divider;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) 	u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) 	val = readl_relaxed(dc->base + DIV_CTRL0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) 	val >>= dc->div_bit_start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 	divider = val & ~(~0 << dc->div_bit_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 	if (dc->divider_table)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 		divider = dc->divider_table[divider];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 	return divider;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) static int dove_calc_divider(const struct dove_clk *dc, unsigned long rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 			     unsigned long parent_rate, bool set)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 	unsigned int divider, max;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 	divider = DIV_ROUND_CLOSEST(parent_rate, rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 	if (dc->divider_table) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 		unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 		for (i = 0; dc->divider_table[i]; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 			if (divider == dc->divider_table[i]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 				divider = i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 				break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 			}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 		if (!dc->divider_table[i])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 			return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 	} else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 		max = 1 << dc->div_bit_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 		if (set && (divider == 0 || divider >= max))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 			return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 		if (divider >= max)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 			divider = max - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 		else if (divider == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 			divider = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 	return divider;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) static unsigned long dove_recalc_rate(struct clk_hw *hw, unsigned long parent)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 	struct dove_clk *dc = to_dove_clk(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 	unsigned int divider = dove_get_divider(dc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 	unsigned long rate = DIV_ROUND_CLOSEST(parent, divider);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 	pr_debug("%s(): %s divider=%u parent=%lu rate=%lu\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 		 __func__, dc->name, divider, parent, rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 	return rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) static long dove_round_rate(struct clk_hw *hw, unsigned long rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 			    unsigned long *parent)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 	struct dove_clk *dc = to_dove_clk(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 	unsigned long parent_rate = *parent;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 	int divider;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 	divider = dove_calc_divider(dc, rate, parent_rate, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 	if (divider < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 		return divider;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 	rate = DIV_ROUND_CLOSEST(parent_rate, divider);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 	pr_debug("%s(): %s divider=%u parent=%lu rate=%lu\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 		 __func__, dc->name, divider, parent_rate, rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 	return rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) static int dove_set_clock(struct clk_hw *hw, unsigned long rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 			  unsigned long parent_rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 	struct dove_clk *dc = to_dove_clk(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 	u32 mask, load, div;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 	int divider;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 	divider = dove_calc_divider(dc, rate, parent_rate, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 	if (divider < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 		return divider;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 	pr_debug("%s(): %s divider=%u parent=%lu rate=%lu\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 		 __func__, dc->name, divider, parent_rate, rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 	div = (u32)divider << dc->div_bit_start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 	mask = ~(~0 << dc->div_bit_size) << dc->div_bit_start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 	load = BIT(dc->div_bit_load);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 	spin_lock(dc->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 	dove_load_divider(dc->base, div, mask, load);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 	spin_unlock(dc->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) static const struct clk_ops dove_divider_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 	.set_rate	= dove_set_clock,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 	.round_rate	= dove_round_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 	.recalc_rate	= dove_recalc_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) static struct clk *clk_register_dove_divider(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 	struct dove_clk *dc, const char **parent_names, size_t num_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 	void __iomem *base)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 	char name[32];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 	struct clk_init_data init = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 		.name = name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 		.ops = &dove_divider_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 		.parent_names = parent_names,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 		.num_parents = num_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 	};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 	strlcpy(name, dc->name, sizeof(name));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 	dc->hw.init = &init;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 	dc->base = base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 	dc->div_bit_size = dc->div_bit_end - dc->div_bit_start + 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 	return clk_register(dev, &dc->hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) static DEFINE_SPINLOCK(dove_divider_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) static u32 axi_divider[] = {-1, 2, 1, 3, 4, 6, 5, 7, 8, 10, 9, 0};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) static struct dove_clk dove_hw_clocks[4] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 	{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 		.name = "axi",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 		.lock = &dove_divider_lock,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 		.div_bit_start = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 		.div_bit_end = 6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 		.div_bit_load = 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 		.divider_table = axi_divider,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 	}, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 		.name = "gpu",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 		.lock = &dove_divider_lock,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 		.div_bit_start = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 		.div_bit_end = 13,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 		.div_bit_load = 14,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 	}, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 		.name = "vmeta",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 		.lock = &dove_divider_lock,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 		.div_bit_start = 15,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 		.div_bit_end = 20,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 		.div_bit_load = 21,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 	}, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 		.name = "lcd",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 		.lock = &dove_divider_lock,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 		.div_bit_start = 22,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 		.div_bit_end = 27,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 		.div_bit_load = 28,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) static const char *core_pll[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 	"core-pll",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) static int dove_divider_init(struct device *dev, void __iomem *base,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 	struct clk **clks)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 	struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 	int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 	 * Create the core PLL clock.  We treat this as a fixed rate
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 	 * clock as we don't know any better, and documentation is sparse.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 	clk = clk_register_fixed_rate(dev, core_pll[0], NULL, 0, 2000000000UL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 	if (IS_ERR(clk))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 		return PTR_ERR(clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 	for (i = 0; i < ARRAY_SIZE(dove_hw_clocks); i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 		clks[i] = clk_register_dove_divider(dev, &dove_hw_clocks[i],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 						    core_pll,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 						    ARRAY_SIZE(core_pll), base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) static struct clk *dove_divider_clocks[4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) static struct clk_onecell_data dove_divider_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 	.clks = dove_divider_clocks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 	.clk_num = ARRAY_SIZE(dove_divider_clocks),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) void __init dove_divider_clk_init(struct device_node *np)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 	void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 	base = of_iomap(np, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) 	if (WARN_ON(!base))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 		return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) 	if (WARN_ON(dove_divider_init(NULL, base, dove_divider_clocks))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) 		iounmap(base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) 		return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) 	of_clk_add_provider(np, of_clk_src_onecell_get, &dove_divider_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) }