^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Marvell Armada CP110 System Controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2016 Marvell
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * CP110 has 6 core clocks:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) * - PLL0 (1 Ghz)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) * - PPv2 core (1/3 PLL0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) * - x2 Core (1/2 PLL0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) * - Core (1/2 x2 Core)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) * - SDIO (2/5 PLL0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) * - NAND clock, which is either:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) * - Equal to SDIO clock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) * - 2/5 PLL0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) * CP110 has 32 gateable clocks, for the various peripherals in the IP.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define pr_fmt(fmt) "cp110-system-controller: " fmt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #include "armada_ap_cp_helper.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #include <linux/clk-provider.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #include <linux/mfd/syscon.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #include <linux/regmap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define CP110_PM_CLOCK_GATING_REG 0x220
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define CP110_NAND_FLASH_CLK_CTRL_REG 0x700
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define NF_CLOCK_SEL_400_MASK BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) CP110_CLK_TYPE_CORE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) CP110_CLK_TYPE_GATABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define CP110_MAX_CORE_CLOCKS 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define CP110_MAX_GATABLE_CLOCKS 32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define CP110_CLK_NUM \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) (CP110_MAX_CORE_CLOCKS + CP110_MAX_GATABLE_CLOCKS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define CP110_CORE_PLL0 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define CP110_CORE_PPV2 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define CP110_CORE_X2CORE 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define CP110_CORE_CORE 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define CP110_CORE_NAND 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define CP110_CORE_SDIO 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) /* A number of gateable clocks need special handling */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define CP110_GATE_AUDIO 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define CP110_GATE_COMM_UNIT 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define CP110_GATE_NAND 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define CP110_GATE_PPV2 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define CP110_GATE_SDIO 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define CP110_GATE_MG 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define CP110_GATE_MG_CORE 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define CP110_GATE_XOR1 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define CP110_GATE_XOR0 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define CP110_GATE_GOP_DP 9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define CP110_GATE_PCIE_X1_0 11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define CP110_GATE_PCIE_X1_1 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define CP110_GATE_PCIE_X4 13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define CP110_GATE_PCIE_XOR 14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define CP110_GATE_SATA 15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define CP110_GATE_SATA_USB 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define CP110_GATE_MAIN 17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define CP110_GATE_SDMMC_GOP 18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define CP110_GATE_SLOW_IO 21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define CP110_GATE_USB3H0 22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define CP110_GATE_USB3H1 23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define CP110_GATE_USB3DEV 24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define CP110_GATE_EIP150 25
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define CP110_GATE_EIP197 26
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) static const char * const gate_base_names[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) [CP110_GATE_AUDIO] = "audio",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) [CP110_GATE_COMM_UNIT] = "communit",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) [CP110_GATE_NAND] = "nand",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) [CP110_GATE_PPV2] = "ppv2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) [CP110_GATE_SDIO] = "sdio",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) [CP110_GATE_MG] = "mg-domain",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) [CP110_GATE_MG_CORE] = "mg-core",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) [CP110_GATE_XOR1] = "xor1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) [CP110_GATE_XOR0] = "xor0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) [CP110_GATE_GOP_DP] = "gop-dp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) [CP110_GATE_PCIE_X1_0] = "pcie_x10",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) [CP110_GATE_PCIE_X1_1] = "pcie_x11",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) [CP110_GATE_PCIE_X4] = "pcie_x4",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) [CP110_GATE_PCIE_XOR] = "pcie-xor",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) [CP110_GATE_SATA] = "sata",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) [CP110_GATE_SATA_USB] = "sata-usb",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) [CP110_GATE_MAIN] = "main",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) [CP110_GATE_SDMMC_GOP] = "sd-mmc-gop",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) [CP110_GATE_SLOW_IO] = "slow-io",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) [CP110_GATE_USB3H0] = "usb3h0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) [CP110_GATE_USB3H1] = "usb3h1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) [CP110_GATE_USB3DEV] = "usb3dev",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) [CP110_GATE_EIP150] = "eip150",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) [CP110_GATE_EIP197] = "eip197"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) struct cp110_gate_clk {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) struct clk_hw hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) struct regmap *regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) u8 bit_idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define to_cp110_gate_clk(hw) container_of(hw, struct cp110_gate_clk, hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) static int cp110_gate_enable(struct clk_hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) struct cp110_gate_clk *gate = to_cp110_gate_clk(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) regmap_update_bits(gate->regmap, CP110_PM_CLOCK_GATING_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) BIT(gate->bit_idx), BIT(gate->bit_idx));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) static void cp110_gate_disable(struct clk_hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) struct cp110_gate_clk *gate = to_cp110_gate_clk(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) regmap_update_bits(gate->regmap, CP110_PM_CLOCK_GATING_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) BIT(gate->bit_idx), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) static int cp110_gate_is_enabled(struct clk_hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) struct cp110_gate_clk *gate = to_cp110_gate_clk(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) regmap_read(gate->regmap, CP110_PM_CLOCK_GATING_REG, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) return val & BIT(gate->bit_idx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) static const struct clk_ops cp110_gate_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) .enable = cp110_gate_enable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) .disable = cp110_gate_disable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) .is_enabled = cp110_gate_is_enabled,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) static struct clk_hw *cp110_register_gate(const char *name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) const char *parent_name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) struct regmap *regmap, u8 bit_idx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) struct cp110_gate_clk *gate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) struct clk_hw *hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) struct clk_init_data init;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) gate = kzalloc(sizeof(*gate), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) if (!gate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) return ERR_PTR(-ENOMEM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) memset(&init, 0, sizeof(init));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) init.name = name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) init.ops = &cp110_gate_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) init.parent_names = &parent_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) init.num_parents = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) gate->regmap = regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) gate->bit_idx = bit_idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) gate->hw.init = &init;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) hw = &gate->hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) ret = clk_hw_register(NULL, hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) kfree(gate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) hw = ERR_PTR(ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) return hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) static void cp110_unregister_gate(struct clk_hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) clk_hw_unregister(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) kfree(to_cp110_gate_clk(hw));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) static struct clk_hw *cp110_of_clk_get(struct of_phandle_args *clkspec,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) void *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) struct clk_hw_onecell_data *clk_data = data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) unsigned int type = clkspec->args[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) unsigned int idx = clkspec->args[1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) if (type == CP110_CLK_TYPE_CORE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) if (idx >= CP110_MAX_CORE_CLOCKS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) return ERR_PTR(-EINVAL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) return clk_data->hws[idx];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) } else if (type == CP110_CLK_TYPE_GATABLE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) if (idx >= CP110_MAX_GATABLE_CLOCKS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) return ERR_PTR(-EINVAL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) return clk_data->hws[CP110_MAX_CORE_CLOCKS + idx];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) return ERR_PTR(-EINVAL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) static int cp110_syscon_common_probe(struct platform_device *pdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) struct device_node *syscon_node)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) struct regmap *regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) struct device *dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) struct device_node *np = dev->of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) const char *ppv2_name, *pll0_name, *core_name, *x2core_name, *nand_name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) *sdio_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) struct clk_hw_onecell_data *cp110_clk_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) struct clk_hw *hw, **cp110_clks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) u32 nand_clk_ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) int i, ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) char *gate_name[ARRAY_SIZE(gate_base_names)];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) regmap = syscon_node_to_regmap(syscon_node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) if (IS_ERR(regmap))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) return PTR_ERR(regmap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) ret = regmap_read(regmap, CP110_NAND_FLASH_CLK_CTRL_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) &nand_clk_ctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) cp110_clk_data = devm_kzalloc(dev, struct_size(cp110_clk_data, hws,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) CP110_CLK_NUM),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) if (!cp110_clk_data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) cp110_clks = cp110_clk_data->hws;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) cp110_clk_data->num = CP110_CLK_NUM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) /* Register the PLL0 which is the root of the hw tree */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) pll0_name = ap_cp_unique_name(dev, syscon_node, "pll0");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) hw = clk_hw_register_fixed_rate(NULL, pll0_name, NULL, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 1000 * 1000 * 1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) if (IS_ERR(hw)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) ret = PTR_ERR(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) goto fail_pll0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) cp110_clks[CP110_CORE_PLL0] = hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) /* PPv2 is PLL0/3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) ppv2_name = ap_cp_unique_name(dev, syscon_node, "ppv2-core");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) hw = clk_hw_register_fixed_factor(NULL, ppv2_name, pll0_name, 0, 1, 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) if (IS_ERR(hw)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) ret = PTR_ERR(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) goto fail_ppv2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) cp110_clks[CP110_CORE_PPV2] = hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) /* X2CORE clock is PLL0/2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) x2core_name = ap_cp_unique_name(dev, syscon_node, "x2core");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) hw = clk_hw_register_fixed_factor(NULL, x2core_name, pll0_name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) 0, 1, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) if (IS_ERR(hw)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) ret = PTR_ERR(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) goto fail_eip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) cp110_clks[CP110_CORE_X2CORE] = hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) /* Core clock is X2CORE/2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) core_name = ap_cp_unique_name(dev, syscon_node, "core");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) hw = clk_hw_register_fixed_factor(NULL, core_name, x2core_name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) 0, 1, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) if (IS_ERR(hw)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) ret = PTR_ERR(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) goto fail_core;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) cp110_clks[CP110_CORE_CORE] = hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) /* NAND can be either PLL0/2.5 or core clock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) nand_name = ap_cp_unique_name(dev, syscon_node, "nand-core");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) if (nand_clk_ctrl & NF_CLOCK_SEL_400_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) hw = clk_hw_register_fixed_factor(NULL, nand_name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) pll0_name, 0, 2, 5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) hw = clk_hw_register_fixed_factor(NULL, nand_name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) core_name, 0, 1, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) if (IS_ERR(hw)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) ret = PTR_ERR(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) goto fail_nand;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) cp110_clks[CP110_CORE_NAND] = hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) /* SDIO clock is PLL0/2.5 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) sdio_name = ap_cp_unique_name(dev, syscon_node, "sdio-core");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) hw = clk_hw_register_fixed_factor(NULL, sdio_name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) pll0_name, 0, 2, 5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) if (IS_ERR(hw)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) ret = PTR_ERR(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) goto fail_sdio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) cp110_clks[CP110_CORE_SDIO] = hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) /* create the unique name for all the gate clocks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) for (i = 0; i < ARRAY_SIZE(gate_base_names); i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) gate_name[i] = ap_cp_unique_name(dev, syscon_node,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) gate_base_names[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) for (i = 0; i < ARRAY_SIZE(gate_base_names); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) const char *parent;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) if (gate_name[i] == NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) switch (i) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) case CP110_GATE_NAND:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) parent = nand_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) case CP110_GATE_MG:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) case CP110_GATE_GOP_DP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) case CP110_GATE_PPV2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) parent = ppv2_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) case CP110_GATE_SDIO:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) parent = sdio_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) case CP110_GATE_MAIN:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) case CP110_GATE_PCIE_XOR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) case CP110_GATE_PCIE_X4:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) case CP110_GATE_EIP150:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) case CP110_GATE_EIP197:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) parent = x2core_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) parent = core_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) hw = cp110_register_gate(gate_name[i], parent, regmap, i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) if (IS_ERR(hw)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) ret = PTR_ERR(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) goto fail_gate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) cp110_clks[CP110_MAX_CORE_CLOCKS + i] = hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) ret = of_clk_add_hw_provider(np, cp110_of_clk_get, cp110_clk_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) goto fail_clk_add;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) platform_set_drvdata(pdev, cp110_clks);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) fail_clk_add:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) fail_gate:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) for (i = 0; i < CP110_MAX_GATABLE_CLOCKS; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) hw = cp110_clks[CP110_MAX_CORE_CLOCKS + i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) if (hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) cp110_unregister_gate(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) clk_hw_unregister_fixed_factor(cp110_clks[CP110_CORE_SDIO]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) fail_sdio:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) clk_hw_unregister_fixed_factor(cp110_clks[CP110_CORE_NAND]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) fail_nand:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) clk_hw_unregister_fixed_factor(cp110_clks[CP110_CORE_CORE]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) fail_core:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) clk_hw_unregister_fixed_factor(cp110_clks[CP110_CORE_X2CORE]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) fail_eip:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) clk_hw_unregister_fixed_factor(cp110_clks[CP110_CORE_PPV2]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) fail_ppv2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) clk_hw_unregister_fixed_rate(cp110_clks[CP110_CORE_PLL0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) fail_pll0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) static int cp110_syscon_legacy_clk_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) dev_warn(&pdev->dev, FW_WARN "Using legacy device tree binding\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) dev_warn(&pdev->dev, FW_WARN "Update your device tree:\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) dev_warn(&pdev->dev, FW_WARN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) "This binding won't be supported in future kernels\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) return cp110_syscon_common_probe(pdev, pdev->dev.of_node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) static int cp110_clk_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) return cp110_syscon_common_probe(pdev, pdev->dev.of_node->parent);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) static const struct of_device_id cp110_syscon_legacy_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) { .compatible = "marvell,cp110-system-controller0", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) static struct platform_driver cp110_syscon_legacy_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) .probe = cp110_syscon_legacy_clk_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) .name = "marvell-cp110-system-controller0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) .of_match_table = cp110_syscon_legacy_of_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) .suppress_bind_attrs = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) builtin_platform_driver(cp110_syscon_legacy_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) static const struct of_device_id cp110_clock_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) { .compatible = "marvell,cp110-clock", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) static struct platform_driver cp110_clock_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) .probe = cp110_clk_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) .name = "marvell-cp110-clock",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) .of_match_table = cp110_clock_of_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) .suppress_bind_attrs = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) builtin_platform_driver(cp110_clock_driver);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
3 Commits
0 Branches
0 Tags