Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) /* SPDX-License-Identifier: GPL-2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3)  * Marvell EBU SoC common clock handling
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5)  * Copyright (C) 2012 Marvell
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7)  * Gregory CLEMENT <gregory.clement@free-electrons.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8)  * Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9)  * Andrew Lunn <andrew@lunn.ch>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #ifndef __CLK_MVEBU_COMMON_H_
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #define __CLK_MVEBU_COMMON_H_
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) extern spinlock_t ctrl_gating_lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) struct device_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) struct coreclk_ratio {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) 	int id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) 	const char *name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) struct coreclk_soc_desc {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) 	u32 (*get_tclk_freq)(void __iomem *sar);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) 	u32 (*get_cpu_freq)(void __iomem *sar);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) 	void (*get_clk_ratio)(void __iomem *sar, int id, int *mult, int *div);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) 	u32 (*get_refclk_freq)(void __iomem *sar);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) 	bool (*is_sscg_enabled)(void __iomem *sar);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) 	u32 (*fix_sscg_deviation)(u32 system_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) 	const struct coreclk_ratio *ratios;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) 	int num_ratios;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) struct clk_gating_soc_desc {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) 	const char *name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) 	const char *parent;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) 	int bit_idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) 	unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) void __init mvebu_coreclk_setup(struct device_node *np,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) 				const struct coreclk_soc_desc *desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) void __init mvebu_clk_gating_setup(struct device_node *np,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) 				   const struct clk_gating_soc_desc *desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52)  * This function is shared among the Kirkwood, Armada 370, Armada XP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53)  * and Armada 375 SoC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) u32 kirkwood_fix_sscg_deviation(u32 system_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #endif