^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Marvell EBU SoC common clock handling
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2012 Marvell
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Gregory CLEMENT <gregory.clement@free-electrons.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * Andrew Lunn <andrew@lunn.ch>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/clk-provider.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/of_address.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/syscore_ops.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include "common.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) * Core Clocks
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define SSCG_CONF_MODE(reg) (((reg) >> 16) & 0x3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define SSCG_SPREAD_DOWN 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define SSCG_SPREAD_UP 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define SSCG_SPREAD_CENTRAL 0x2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define SSCG_CONF_LOW(reg) (((reg) >> 8) & 0xFF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define SSCG_CONF_HIGH(reg) ((reg) & 0xFF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) static struct clk_onecell_data clk_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) * This function can be used by the Kirkwood, the Armada 370, the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) * Armada XP and the Armada 375 SoC. The name of the function was
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) * chosen following the dt convention: using the first known SoC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) * compatible with it.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) u32 kirkwood_fix_sscg_deviation(u32 system_clk)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) struct device_node *sscg_np = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) void __iomem *sscg_map;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) u32 sscg_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) s32 low_bound, high_bound;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) u64 freq_swing_half;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) sscg_np = of_find_node_by_name(NULL, "sscg");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) if (sscg_np == NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) pr_err("cannot get SSCG register node\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) return system_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) sscg_map = of_iomap(sscg_np, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) if (sscg_map == NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) pr_err("cannot map SSCG register\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) sscg_reg = readl(sscg_map);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) high_bound = SSCG_CONF_HIGH(sscg_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) low_bound = SSCG_CONF_LOW(sscg_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) if ((high_bound - low_bound) <= 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) * From Marvell engineer we got the following formula (when
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) * this code was written, the datasheet was erroneous)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) * Spread percentage = 1/96 * (H - L) / H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) * H = SSCG_High_Boundary
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) * L = SSCG_Low_Boundary
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) * As the deviation is half of spread then it lead to the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) * following formula in the code.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) * To avoid an overflow and not lose any significant digit in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) * the same time we have to use a 64 bit integer.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) freq_swing_half = (((u64)high_bound - (u64)low_bound)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) * (u64)system_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) do_div(freq_swing_half, (2 * 96 * high_bound));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) switch (SSCG_CONF_MODE(sscg_reg)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) case SSCG_SPREAD_DOWN:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) system_clk -= freq_swing_half;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) case SSCG_SPREAD_UP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) system_clk += freq_swing_half;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) case SSCG_SPREAD_CENTRAL:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) iounmap(sscg_map);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) of_node_put(sscg_np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) return system_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) void __init mvebu_coreclk_setup(struct device_node *np,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) const struct coreclk_soc_desc *desc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) const char *tclk_name = "tclk";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) const char *cpuclk_name = "cpuclk";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) unsigned long rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) int n;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) base = of_iomap(np, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) if (WARN_ON(!base))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) /* Allocate struct for TCLK, cpu clk, and core ratio clocks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) clk_data.clk_num = 2 + desc->num_ratios;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) /* One more clock for the optional refclk */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) if (desc->get_refclk_freq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) clk_data.clk_num += 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) clk_data.clks = kcalloc(clk_data.clk_num, sizeof(*clk_data.clks),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) if (WARN_ON(!clk_data.clks)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) iounmap(base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) /* Register TCLK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) of_property_read_string_index(np, "clock-output-names", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) &tclk_name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) rate = desc->get_tclk_freq(base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) clk_data.clks[0] = clk_register_fixed_rate(NULL, tclk_name, NULL, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) WARN_ON(IS_ERR(clk_data.clks[0]));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) /* Register CPU clock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) of_property_read_string_index(np, "clock-output-names", 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) &cpuclk_name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) rate = desc->get_cpu_freq(base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) if (desc->is_sscg_enabled && desc->fix_sscg_deviation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) && desc->is_sscg_enabled(base))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) rate = desc->fix_sscg_deviation(rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) clk_data.clks[1] = clk_register_fixed_rate(NULL, cpuclk_name, NULL, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) WARN_ON(IS_ERR(clk_data.clks[1]));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) /* Register fixed-factor clocks derived from CPU clock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) for (n = 0; n < desc->num_ratios; n++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) const char *rclk_name = desc->ratios[n].name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) int mult, div;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) of_property_read_string_index(np, "clock-output-names",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 2+n, &rclk_name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) desc->get_clk_ratio(base, desc->ratios[n].id, &mult, &div);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) clk_data.clks[2+n] = clk_register_fixed_factor(NULL, rclk_name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) cpuclk_name, 0, mult, div);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) WARN_ON(IS_ERR(clk_data.clks[2+n]));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) /* Register optional refclk */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) if (desc->get_refclk_freq) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) const char *name = "refclk";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) of_property_read_string_index(np, "clock-output-names",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 2 + desc->num_ratios, &name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) rate = desc->get_refclk_freq(base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) clk_data.clks[2 + desc->num_ratios] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) clk_register_fixed_rate(NULL, name, NULL, 0, rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) WARN_ON(IS_ERR(clk_data.clks[2 + desc->num_ratios]));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) /* SAR register isn't needed anymore */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) iounmap(base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) * Clock Gating Control
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) DEFINE_SPINLOCK(ctrl_gating_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) struct clk_gating_ctrl {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) spinlock_t *lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) struct clk **gates;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) int num_gates;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) u32 saved_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) static struct clk_gating_ctrl *ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) static struct clk *clk_gating_get_src(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) struct of_phandle_args *clkspec, void *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) int n;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) if (clkspec->args_count < 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) return ERR_PTR(-EINVAL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) for (n = 0; n < ctrl->num_gates; n++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) struct clk_gate *gate =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) to_clk_gate(__clk_get_hw(ctrl->gates[n]));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) if (clkspec->args[0] == gate->bit_idx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) return ctrl->gates[n];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) return ERR_PTR(-ENODEV);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) static int mvebu_clk_gating_suspend(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) ctrl->saved_reg = readl(ctrl->base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) static void mvebu_clk_gating_resume(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) writel(ctrl->saved_reg, ctrl->base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) static struct syscore_ops clk_gate_syscore_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) .suspend = mvebu_clk_gating_suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) .resume = mvebu_clk_gating_resume,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) void __init mvebu_clk_gating_setup(struct device_node *np,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) const struct clk_gating_soc_desc *desc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) const char *default_parent = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) int n;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) if (ctrl) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) pr_err("mvebu-clk-gating: cannot instantiate more than one gateable clock device\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) base = of_iomap(np, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) if (WARN_ON(!base))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) clk = of_clk_get(np, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) if (!IS_ERR(clk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) default_parent = __clk_get_name(clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) clk_put(clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) ctrl = kzalloc(sizeof(*ctrl), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) if (WARN_ON(!ctrl))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) goto ctrl_out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) /* lock must already be initialized */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) ctrl->lock = &ctrl_gating_lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) ctrl->base = base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) /* Count, allocate, and register clock gates */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) for (n = 0; desc[n].name;)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) n++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) ctrl->num_gates = n;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) ctrl->gates = kcalloc(ctrl->num_gates, sizeof(*ctrl->gates),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) if (WARN_ON(!ctrl->gates))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) goto gates_out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) for (n = 0; n < ctrl->num_gates; n++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) const char *parent =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) (desc[n].parent) ? desc[n].parent : default_parent;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) ctrl->gates[n] = clk_register_gate(NULL, desc[n].name, parent,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) desc[n].flags, base, desc[n].bit_idx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) 0, ctrl->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) WARN_ON(IS_ERR(ctrl->gates[n]));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) of_clk_add_provider(np, clk_gating_get_src, ctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) register_syscore_ops(&clk_gate_syscore_ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) gates_out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) kfree(ctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) ctrl_out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) iounmap(base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) }
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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