^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Marvell Armada XP SoC clocks
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2012 Marvell
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Gregory CLEMENT <gregory.clement@free-electrons.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * Andrew Lunn <andrew@lunn.ch>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/clk-provider.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include "common.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) * Core Clocks
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) * Armada XP Sample At Reset is a 64 bit bitfiled split in two
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) * register of 32 bits
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define SARL 0 /* Low part [0:31] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define SARL_AXP_PCLK_FREQ_OPT 21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define SARL_AXP_PCLK_FREQ_OPT_MASK 0x7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define SARL_AXP_FAB_FREQ_OPT 24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define SARL_AXP_FAB_FREQ_OPT_MASK 0xF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define SARH 4 /* High part [32:63] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define SARH_AXP_PCLK_FREQ_OPT (52-32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define SARH_AXP_PCLK_FREQ_OPT_MASK 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define SARH_AXP_PCLK_FREQ_OPT_SHIFT 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define SARH_AXP_FAB_FREQ_OPT (51-32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define SARH_AXP_FAB_FREQ_OPT_MASK 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define SARH_AXP_FAB_FREQ_OPT_SHIFT 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) enum { AXP_CPU_TO_NBCLK, AXP_CPU_TO_HCLK, AXP_CPU_TO_DRAMCLK };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) static const struct coreclk_ratio axp_coreclk_ratios[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) { .id = AXP_CPU_TO_NBCLK, .name = "nbclk" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) { .id = AXP_CPU_TO_HCLK, .name = "hclk" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) { .id = AXP_CPU_TO_DRAMCLK, .name = "dramclk" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) /* Armada XP TCLK frequency is fixed to 250MHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) static u32 __init axp_get_tclk_freq(void __iomem *sar)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) return 250000000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) static const u32 axp_cpu_freqs[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) 1000000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) 1066000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) 1200000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) 1333000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) 1500000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) 1666000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) 1800000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) 2000000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) 667000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) 800000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) 1600000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) static u32 __init axp_get_cpu_freq(void __iomem *sar)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) u32 cpu_freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) u8 cpu_freq_select = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) cpu_freq_select = ((readl(sar + SARL) >> SARL_AXP_PCLK_FREQ_OPT) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) SARL_AXP_PCLK_FREQ_OPT_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) * The upper bit is not contiguous to the other ones and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) * located in the high part of the SAR registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) cpu_freq_select |= (((readl(sar + SARH) >> SARH_AXP_PCLK_FREQ_OPT) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) SARH_AXP_PCLK_FREQ_OPT_MASK) << SARH_AXP_PCLK_FREQ_OPT_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) if (cpu_freq_select >= ARRAY_SIZE(axp_cpu_freqs)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) pr_err("CPU freq select unsupported: %d\n", cpu_freq_select);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) cpu_freq = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) } else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) cpu_freq = axp_cpu_freqs[cpu_freq_select];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) return cpu_freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) static const int axp_nbclk_ratios[32][2] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) {0, 1}, {1, 2}, {2, 2}, {2, 2},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) {1, 2}, {1, 2}, {1, 1}, {2, 3},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) {0, 1}, {1, 2}, {2, 4}, {0, 1},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) {1, 2}, {0, 1}, {0, 1}, {2, 2},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) {0, 1}, {0, 1}, {0, 1}, {1, 1},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) {2, 3}, {0, 1}, {0, 1}, {0, 1},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) {0, 1}, {0, 1}, {0, 1}, {1, 1},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) {0, 1}, {0, 1}, {0, 1}, {0, 1},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) static const int axp_hclk_ratios[32][2] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) {0, 1}, {1, 2}, {2, 6}, {2, 3},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) {1, 3}, {1, 4}, {1, 2}, {2, 6},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) {0, 1}, {1, 6}, {2, 10}, {0, 1},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) {1, 4}, {0, 1}, {0, 1}, {2, 5},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) {0, 1}, {0, 1}, {0, 1}, {1, 2},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) {2, 6}, {0, 1}, {0, 1}, {0, 1},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) {0, 1}, {0, 1}, {0, 1}, {1, 1},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) {0, 1}, {0, 1}, {0, 1}, {0, 1},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) static const int axp_dramclk_ratios[32][2] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) {0, 1}, {1, 2}, {2, 3}, {2, 3},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) {1, 3}, {1, 2}, {1, 2}, {2, 6},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) {0, 1}, {1, 3}, {2, 5}, {0, 1},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) {1, 4}, {0, 1}, {0, 1}, {2, 5},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) {0, 1}, {0, 1}, {0, 1}, {1, 1},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) {2, 3}, {0, 1}, {0, 1}, {0, 1},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) {0, 1}, {0, 1}, {0, 1}, {1, 1},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) {0, 1}, {0, 1}, {0, 1}, {0, 1},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) static void __init axp_get_clk_ratio(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) void __iomem *sar, int id, int *mult, int *div)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) u32 opt = ((readl(sar + SARL) >> SARL_AXP_FAB_FREQ_OPT) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) SARL_AXP_FAB_FREQ_OPT_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) * The upper bit is not contiguous to the other ones and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) * located in the high part of the SAR registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) opt |= (((readl(sar + SARH) >> SARH_AXP_FAB_FREQ_OPT) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) SARH_AXP_FAB_FREQ_OPT_MASK) << SARH_AXP_FAB_FREQ_OPT_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) switch (id) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) case AXP_CPU_TO_NBCLK:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) *mult = axp_nbclk_ratios[opt][0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) *div = axp_nbclk_ratios[opt][1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) case AXP_CPU_TO_HCLK:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) *mult = axp_hclk_ratios[opt][0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) *div = axp_hclk_ratios[opt][1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) case AXP_CPU_TO_DRAMCLK:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) *mult = axp_dramclk_ratios[opt][0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) *div = axp_dramclk_ratios[opt][1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) static const struct coreclk_soc_desc axp_coreclks = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) .get_tclk_freq = axp_get_tclk_freq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) .get_cpu_freq = axp_get_cpu_freq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) .get_clk_ratio = axp_get_clk_ratio,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) .ratios = axp_coreclk_ratios,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) .num_ratios = ARRAY_SIZE(axp_coreclk_ratios),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) * Clock Gating Control
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) static const struct clk_gating_soc_desc axp_gating_desc[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) { "audio", NULL, 0, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) { "ge3", NULL, 1, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) { "ge2", NULL, 2, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) { "ge1", NULL, 3, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) { "ge0", NULL, 4, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) { "pex00", NULL, 5, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) { "pex01", NULL, 6, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) { "pex02", NULL, 7, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) { "pex03", NULL, 8, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) { "pex10", NULL, 9, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) { "pex11", NULL, 10, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) { "pex12", NULL, 11, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) { "pex13", NULL, 12, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) { "bp", NULL, 13, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) { "sata0lnk", NULL, 14, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) { "sata0", "sata0lnk", 15, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) { "lcd", NULL, 16, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) { "sdio", NULL, 17, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) { "usb0", NULL, 18, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) { "usb1", NULL, 19, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) { "usb2", NULL, 20, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) { "xor0", NULL, 22, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) { "crypto", NULL, 23, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) { "tdm", NULL, 25, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) { "pex20", NULL, 26, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) { "pex30", NULL, 27, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) { "xor1", NULL, 28, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) { "sata1lnk", NULL, 29, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) { "sata1", "sata1lnk", 30, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) static void __init axp_clk_init(struct device_node *np)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) struct device_node *cgnp =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) of_find_compatible_node(NULL, NULL, "marvell,armada-xp-gating-clock");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) mvebu_coreclk_setup(np, &axp_coreclks);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) if (cgnp) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) mvebu_clk_gating_setup(cgnp, axp_gating_desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) of_node_put(cgnp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) CLK_OF_DECLARE(axp_clk, "marvell,armada-xp-core-clock", axp_clk_init);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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