^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Marvell Armada 39x SoC clocks
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2015 Marvell
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Gregory CLEMENT <gregory.clement@free-electrons.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * Andrew Lunn <andrew@lunn.ch>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/clk-provider.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include "common.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) * SARL[14:10] : Ratios between CPU, NBCLK, HCLK and DCLK.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) * SARL[15] : TCLK frequency
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) * 0 = 250 MHz
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) * 1 = 200 MHz
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) * SARH[0] : Reference clock frequency
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) * 0 = 25 Mhz
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) * 1 = 40 Mhz
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define SARL 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define SARL_A390_TCLK_FREQ_OPT 15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define SARL_A390_TCLK_FREQ_OPT_MASK 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define SARL_A390_CPU_DDR_L2_FREQ_OPT 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define SARL_A390_CPU_DDR_L2_FREQ_OPT_MASK 0x1F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define SARH 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define SARH_A390_REFCLK_FREQ BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) static const u32 armada_39x_tclk_frequencies[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) 250000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) 200000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) static u32 __init armada_39x_get_tclk_freq(void __iomem *sar)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) u8 tclk_freq_select;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) tclk_freq_select = ((readl(sar + SARL) >> SARL_A390_TCLK_FREQ_OPT) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) SARL_A390_TCLK_FREQ_OPT_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) return armada_39x_tclk_frequencies[tclk_freq_select];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) static const u32 armada_39x_cpu_frequencies[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) [0x0] = 666 * 1000 * 1000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) [0x2] = 800 * 1000 * 1000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) [0x3] = 800 * 1000 * 1000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) [0x4] = 1066 * 1000 * 1000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) [0x5] = 1066 * 1000 * 1000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) [0x6] = 1200 * 1000 * 1000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) [0x8] = 1332 * 1000 * 1000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) [0xB] = 1600 * 1000 * 1000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) [0xC] = 1600 * 1000 * 1000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) [0x12] = 1800 * 1000 * 1000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) [0x1E] = 1800 * 1000 * 1000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) static u32 __init armada_39x_get_cpu_freq(void __iomem *sar)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) u8 cpu_freq_select;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) cpu_freq_select = ((readl(sar + SARL) >> SARL_A390_CPU_DDR_L2_FREQ_OPT) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) SARL_A390_CPU_DDR_L2_FREQ_OPT_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) if (cpu_freq_select >= ARRAY_SIZE(armada_39x_cpu_frequencies)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) pr_err("Selected CPU frequency (%d) unsupported\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) cpu_freq_select);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) return armada_39x_cpu_frequencies[cpu_freq_select];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) enum { A390_CPU_TO_NBCLK, A390_CPU_TO_HCLK, A390_CPU_TO_DCLK };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) static const struct coreclk_ratio armada_39x_coreclk_ratios[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) { .id = A390_CPU_TO_NBCLK, .name = "nbclk" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) { .id = A390_CPU_TO_HCLK, .name = "hclk" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) { .id = A390_CPU_TO_DCLK, .name = "dclk" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) static void __init armada_39x_get_clk_ratio(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) void __iomem *sar, int id, int *mult, int *div)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) switch (id) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) case A390_CPU_TO_NBCLK:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) *mult = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) *div = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) case A390_CPU_TO_HCLK:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) *mult = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) *div = 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) case A390_CPU_TO_DCLK:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) *mult = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) *div = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) static u32 __init armada_39x_refclk_ratio(void __iomem *sar)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) if (readl(sar + SARH) & SARH_A390_REFCLK_FREQ)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) return 40 * 1000 * 1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) return 25 * 1000 * 1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) static const struct coreclk_soc_desc armada_39x_coreclks = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) .get_tclk_freq = armada_39x_get_tclk_freq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) .get_cpu_freq = armada_39x_get_cpu_freq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) .get_clk_ratio = armada_39x_get_clk_ratio,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) .get_refclk_freq = armada_39x_refclk_ratio,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) .ratios = armada_39x_coreclk_ratios,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) .num_ratios = ARRAY_SIZE(armada_39x_coreclk_ratios),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) static void __init armada_39x_coreclk_init(struct device_node *np)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) mvebu_coreclk_setup(np, &armada_39x_coreclks);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) CLK_OF_DECLARE(armada_39x_core_clk, "marvell,armada-390-core-clock",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) armada_39x_coreclk_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) * Clock Gating Control
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) static const struct clk_gating_soc_desc armada_39x_gating_desc[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) { "pex1", NULL, 5 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) { "pex2", NULL, 6 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) { "pex3", NULL, 7 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) { "pex0", NULL, 8 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) { "usb3h0", NULL, 9 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) { "usb3h1", NULL, 10 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) { "sata0", NULL, 15 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) { "sdio", NULL, 17 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) { "xor0", NULL, 22 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) { "xor1", NULL, 28 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) static void __init armada_39x_clk_gating_init(struct device_node *np)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) mvebu_clk_gating_setup(np, armada_39x_gating_desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) CLK_OF_DECLARE(armada_39x_clk_gating, "marvell,armada-390-gating-clock",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) armada_39x_clk_gating_init);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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