^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Marvell Armada 380/385 SoC clocks
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2014 Marvell
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Gregory CLEMENT <gregory.clement@free-electrons.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * Andrew Lunn <andrew@lunn.ch>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/clk-provider.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include "common.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) * SAR[14:10] : Ratios between PCLK0, NBCLK, HCLK and DRAM clocks
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) * SAR[15] : TCLK frequency
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) * 0 = 250 MHz
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) * 1 = 200 MHz
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define SAR_A380_TCLK_FREQ_OPT 15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define SAR_A380_TCLK_FREQ_OPT_MASK 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define SAR_A380_CPU_DDR_L2_FREQ_OPT 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define SAR_A380_CPU_DDR_L2_FREQ_OPT_MASK 0x1F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) static const u32 armada_38x_tclk_frequencies[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) 250000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) 200000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) static u32 __init armada_38x_get_tclk_freq(void __iomem *sar)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) u8 tclk_freq_select;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) tclk_freq_select = ((readl(sar) >> SAR_A380_TCLK_FREQ_OPT) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) SAR_A380_TCLK_FREQ_OPT_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) return armada_38x_tclk_frequencies[tclk_freq_select];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) static const u32 armada_38x_cpu_frequencies[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) 666 * 1000 * 1000, 0, 800 * 1000 * 1000, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) 1066 * 1000 * 1000, 0, 1200 * 1000 * 1000, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) 1332 * 1000 * 1000, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) 1600 * 1000 * 1000, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) 1866 * 1000 * 1000, 0, 0, 2000 * 1000 * 1000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) static u32 __init armada_38x_get_cpu_freq(void __iomem *sar)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) u8 cpu_freq_select;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) cpu_freq_select = ((readl(sar) >> SAR_A380_CPU_DDR_L2_FREQ_OPT) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) SAR_A380_CPU_DDR_L2_FREQ_OPT_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) if (cpu_freq_select >= ARRAY_SIZE(armada_38x_cpu_frequencies)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) pr_err("Selected CPU frequency (%d) unsupported\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) cpu_freq_select);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) return armada_38x_cpu_frequencies[cpu_freq_select];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) enum { A380_CPU_TO_DDR, A380_CPU_TO_L2 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) static const struct coreclk_ratio armada_38x_coreclk_ratios[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) { .id = A380_CPU_TO_L2, .name = "l2clk" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) { .id = A380_CPU_TO_DDR, .name = "ddrclk" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) static const int armada_38x_cpu_l2_ratios[32][2] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) {1, 2}, {0, 1}, {1, 2}, {0, 1},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) {1, 2}, {0, 1}, {1, 2}, {0, 1},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) {1, 2}, {0, 1}, {0, 1}, {0, 1},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) {1, 2}, {0, 1}, {0, 1}, {0, 1},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) {1, 2}, {0, 1}, {0, 1}, {1, 2},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) {0, 1}, {0, 1}, {0, 1}, {0, 1},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) {0, 1}, {0, 1}, {0, 1}, {0, 1},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) {0, 1}, {0, 1}, {0, 1}, {0, 1},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) static const int armada_38x_cpu_ddr_ratios[32][2] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) {0, 1}, {0, 1}, {0, 1}, {0, 1},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) {1, 2}, {0, 1}, {0, 1}, {0, 1},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) {1, 2}, {0, 1}, {0, 1}, {0, 1},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) {1, 2}, {0, 1}, {0, 1}, {0, 1},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) {1, 2}, {0, 1}, {0, 1}, {7, 15},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) {0, 1}, {0, 1}, {0, 1}, {0, 1},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) {0, 1}, {0, 1}, {0, 1}, {0, 1},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) {0, 1}, {0, 1}, {0, 1}, {0, 1},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) static void __init armada_38x_get_clk_ratio(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) void __iomem *sar, int id, int *mult, int *div)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) u32 opt = ((readl(sar) >> SAR_A380_CPU_DDR_L2_FREQ_OPT) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) SAR_A380_CPU_DDR_L2_FREQ_OPT_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) switch (id) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) case A380_CPU_TO_L2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) *mult = armada_38x_cpu_l2_ratios[opt][0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) *div = armada_38x_cpu_l2_ratios[opt][1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) case A380_CPU_TO_DDR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) *mult = armada_38x_cpu_ddr_ratios[opt][0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) *div = armada_38x_cpu_ddr_ratios[opt][1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) static const struct coreclk_soc_desc armada_38x_coreclks = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) .get_tclk_freq = armada_38x_get_tclk_freq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) .get_cpu_freq = armada_38x_get_cpu_freq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) .get_clk_ratio = armada_38x_get_clk_ratio,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) .ratios = armada_38x_coreclk_ratios,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) .num_ratios = ARRAY_SIZE(armada_38x_coreclk_ratios),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) static void __init armada_38x_coreclk_init(struct device_node *np)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) mvebu_coreclk_setup(np, &armada_38x_coreclks);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) CLK_OF_DECLARE(armada_38x_core_clk, "marvell,armada-380-core-clock",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) armada_38x_coreclk_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) * Clock Gating Control
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) static const struct clk_gating_soc_desc armada_38x_gating_desc[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) { "audio", NULL, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) { "ge2", NULL, 2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) { "ge1", NULL, 3 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) { "ge0", NULL, 4 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) { "pex1", NULL, 5 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) { "pex2", NULL, 6 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) { "pex3", NULL, 7 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) { "pex0", NULL, 8 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) { "usb3h0", NULL, 9 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) { "usb3h1", NULL, 10 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) { "usb3d", NULL, 11 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) { "bm", NULL, 13 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) { "crypto0z", NULL, 14 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) { "sata0", NULL, 15 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) { "crypto1z", NULL, 16 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) { "sdio", NULL, 17 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) { "usb2", NULL, 18 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) { "crypto1", NULL, 21 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) { "xor0", NULL, 22 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) { "crypto0", NULL, 23 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) { "tdm", NULL, 25 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) { "xor1", NULL, 28 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) { "sata1", NULL, 30 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) static void __init armada_38x_clk_gating_init(struct device_node *np)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) mvebu_clk_gating_setup(np, armada_38x_gating_desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) CLK_OF_DECLARE(armada_38x_clk_gating, "marvell,armada-380-gating-clock",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) armada_38x_clk_gating_init);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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