Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3)  * Marvell Armada 37xx SoC xtal clocks
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5)  * Copyright (C) 2016 Marvell
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7)  * Gregory CLEMENT <gregory.clement@free-electrons.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/clk-provider.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/mfd/syscon.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/regmap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define NB_GPIO1_LATCH	0x8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define XTAL_MODE	    BIT(9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) static int armada_3700_xtal_clock_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) 	struct device_node *np = pdev->dev.of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) 	const char *xtal_name = "xtal";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) 	struct device_node *parent;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) 	struct regmap *regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) 	struct clk_hw *xtal_hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) 	unsigned int rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) 	u32 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) 	xtal_hw = devm_kzalloc(&pdev->dev, sizeof(*xtal_hw), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) 	if (!xtal_hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) 		return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) 	platform_set_drvdata(pdev, xtal_hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) 	parent = np->parent;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) 	if (!parent) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) 		dev_err(&pdev->dev, "no parent\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) 		return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) 	regmap = syscon_node_to_regmap(parent);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) 	if (IS_ERR(regmap)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) 		dev_err(&pdev->dev, "cannot get regmap\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) 		return PTR_ERR(regmap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) 	ret = regmap_read(regmap, NB_GPIO1_LATCH, &reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) 	if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) 		dev_err(&pdev->dev, "cannot read from regmap\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) 	if (reg & XTAL_MODE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) 		rate = 40000000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) 	else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) 		rate = 25000000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) 	of_property_read_string_index(np, "clock-output-names", 0, &xtal_name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) 	xtal_hw = clk_hw_register_fixed_rate(NULL, xtal_name, NULL, 0, rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) 	if (IS_ERR(xtal_hw))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) 		return PTR_ERR(xtal_hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) 	ret = of_clk_add_hw_provider(np, of_clk_hw_simple_get, xtal_hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) 	return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) static int armada_3700_xtal_clock_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) 	of_clk_del_provider(pdev->dev.of_node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) static const struct of_device_id armada_3700_xtal_clock_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) 	{ .compatible = "marvell,armada-3700-xtal-clock", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) 	{ }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) static struct platform_driver armada_3700_xtal_clock_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) 	.probe = armada_3700_xtal_clock_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) 	.remove = armada_3700_xtal_clock_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) 	.driver		= {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) 		.name	= "marvell-armada-3700-xtal-clock",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) 		.of_match_table = armada_3700_xtal_clock_of_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) builtin_platform_driver(armada_3700_xtal_clock_driver);