^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Marvell Armada 375 SoC clocks
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2014 Marvell
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Gregory CLEMENT <gregory.clement@free-electrons.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * Andrew Lunn <andrew@lunn.ch>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/clk-provider.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include "common.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) * Core Clocks
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) * For the Armada 375 SoCs, the CPU, DDR and L2 clocks frequencies are
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) * all modified at the same time, and not separately as for the Armada
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) * 370 or the Armada XP SoCs.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) * SAR1[21:17] : CPU frequency DDR frequency L2 frequency
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) * 6 = 400 MHz 400 MHz 200 MHz
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) * 15 = 600 MHz 600 MHz 300 MHz
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) * 21 = 800 MHz 534 MHz 400 MHz
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) * 25 = 1000 MHz 500 MHz 500 MHz
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) * others reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) * SAR1[22] : TCLK frequency
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) * 0 = 166 MHz
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) * 1 = 200 MHz
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define SAR1_A375_TCLK_FREQ_OPT 22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define SAR1_A375_TCLK_FREQ_OPT_MASK 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define SAR1_A375_CPU_DDR_L2_FREQ_OPT 17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define SAR1_A375_CPU_DDR_L2_FREQ_OPT_MASK 0x1F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) static const u32 armada_375_tclk_frequencies[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) 166000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) 200000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) static u32 __init armada_375_get_tclk_freq(void __iomem *sar)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) u8 tclk_freq_select;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) tclk_freq_select = ((readl(sar) >> SAR1_A375_TCLK_FREQ_OPT) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) SAR1_A375_TCLK_FREQ_OPT_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) return armada_375_tclk_frequencies[tclk_freq_select];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) static const u32 armada_375_cpu_frequencies[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) 0, 0, 0, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) 400000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) 0, 0, 0, 0, 0, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) 600000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) 0, 0, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) 800000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) 1000000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) static u32 __init armada_375_get_cpu_freq(void __iomem *sar)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) u8 cpu_freq_select;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) cpu_freq_select = ((readl(sar) >> SAR1_A375_CPU_DDR_L2_FREQ_OPT) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) SAR1_A375_CPU_DDR_L2_FREQ_OPT_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) if (cpu_freq_select >= ARRAY_SIZE(armada_375_cpu_frequencies)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) pr_err("Selected CPU frequency (%d) unsupported\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) cpu_freq_select);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) } else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) return armada_375_cpu_frequencies[cpu_freq_select];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) enum { A375_CPU_TO_DDR, A375_CPU_TO_L2 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) static const struct coreclk_ratio armada_375_coreclk_ratios[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) { .id = A375_CPU_TO_L2, .name = "l2clk" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) { .id = A375_CPU_TO_DDR, .name = "ddrclk" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) static const int armada_375_cpu_l2_ratios[32][2] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) {0, 1}, {0, 1}, {0, 1}, {0, 1},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) {0, 1}, {0, 1}, {1, 2}, {0, 1},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) {0, 1}, {0, 1}, {0, 1}, {0, 1},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) {0, 1}, {0, 1}, {0, 1}, {1, 2},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) {0, 1}, {0, 1}, {0, 1}, {0, 1},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) {0, 1}, {1, 2}, {0, 1}, {0, 1},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) {0, 1}, {1, 2}, {0, 1}, {0, 1},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) {0, 1}, {0, 1}, {0, 1}, {0, 1},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) static const int armada_375_cpu_ddr_ratios[32][2] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) {0, 1}, {0, 1}, {0, 1}, {0, 1},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) {0, 1}, {0, 1}, {1, 1}, {0, 1},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) {0, 1}, {0, 1}, {0, 1}, {0, 1},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) {0, 1}, {0, 1}, {0, 1}, {2, 3},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) {0, 1}, {0, 1}, {0, 1}, {0, 1},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) {0, 1}, {2, 3}, {0, 1}, {0, 1},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) {0, 1}, {1, 2}, {0, 1}, {0, 1},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) {0, 1}, {0, 1}, {0, 1}, {0, 1},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) static void __init armada_375_get_clk_ratio(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) void __iomem *sar, int id, int *mult, int *div)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) u32 opt = ((readl(sar) >> SAR1_A375_CPU_DDR_L2_FREQ_OPT) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) SAR1_A375_CPU_DDR_L2_FREQ_OPT_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) switch (id) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) case A375_CPU_TO_L2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) *mult = armada_375_cpu_l2_ratios[opt][0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) *div = armada_375_cpu_l2_ratios[opt][1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) case A375_CPU_TO_DDR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) *mult = armada_375_cpu_ddr_ratios[opt][0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) *div = armada_375_cpu_ddr_ratios[opt][1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) static const struct coreclk_soc_desc armada_375_coreclks = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) .get_tclk_freq = armada_375_get_tclk_freq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) .get_cpu_freq = armada_375_get_cpu_freq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) .get_clk_ratio = armada_375_get_clk_ratio,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) .ratios = armada_375_coreclk_ratios,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) .num_ratios = ARRAY_SIZE(armada_375_coreclk_ratios),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) static void __init armada_375_coreclk_init(struct device_node *np)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) mvebu_coreclk_setup(np, &armada_375_coreclks);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) CLK_OF_DECLARE(armada_375_core_clk, "marvell,armada-375-core-clock",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) armada_375_coreclk_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) * Clock Gating Control
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) static const struct clk_gating_soc_desc armada_375_gating_desc[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) { "mu", NULL, 2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) { "pp", NULL, 3 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) { "ptp", NULL, 4 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) { "pex0", NULL, 5 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) { "pex1", NULL, 6 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) { "audio", NULL, 8 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) { "nd_clk", "nand", 11 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) { "sata0_link", "sata0_core", 14 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) { "sata0_core", NULL, 15 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) { "usb3", NULL, 16 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) { "sdio", NULL, 17 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) { "usb", NULL, 18 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) { "gop", NULL, 19 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) { "sata1_link", "sata1_core", 20 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) { "sata1_core", NULL, 21 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) { "xor0", NULL, 22 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) { "xor1", NULL, 23 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) { "copro", NULL, 24 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) { "tdm", NULL, 25 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) { "crypto0_enc", NULL, 28 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) { "crypto0_core", NULL, 29 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) { "crypto1_enc", NULL, 30 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) { "crypto1_core", NULL, 31 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) static void __init armada_375_clk_gating_init(struct device_node *np)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) mvebu_clk_gating_setup(np, armada_375_gating_desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) CLK_OF_DECLARE(armada_375_clk_gating, "marvell,armada-375-gating-clock",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) armada_375_clk_gating_init);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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