^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Marvell Armada 370 SoC clocks
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2012 Marvell
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Gregory CLEMENT <gregory.clement@free-electrons.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * Andrew Lunn <andrew@lunn.ch>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/clk-provider.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include "common.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) * Core Clocks
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define SARL 0 /* Low part [0:31] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define SARL_A370_SSCG_ENABLE BIT(10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define SARL_A370_PCLK_FREQ_OPT 11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define SARL_A370_PCLK_FREQ_OPT_MASK 0xF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define SARL_A370_FAB_FREQ_OPT 15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define SARL_A370_FAB_FREQ_OPT_MASK 0x1F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define SARL_A370_TCLK_FREQ_OPT 20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define SARL_A370_TCLK_FREQ_OPT_MASK 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) enum { A370_CPU_TO_NBCLK, A370_CPU_TO_HCLK, A370_CPU_TO_DRAMCLK };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) static const struct coreclk_ratio a370_coreclk_ratios[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) { .id = A370_CPU_TO_NBCLK, .name = "nbclk" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) { .id = A370_CPU_TO_HCLK, .name = "hclk" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) { .id = A370_CPU_TO_DRAMCLK, .name = "dramclk" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) static const u32 a370_tclk_freqs[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) 166000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) 200000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) static u32 __init a370_get_tclk_freq(void __iomem *sar)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) u8 tclk_freq_select = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) tclk_freq_select = ((readl(sar) >> SARL_A370_TCLK_FREQ_OPT) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) SARL_A370_TCLK_FREQ_OPT_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) return a370_tclk_freqs[tclk_freq_select];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) static const u32 a370_cpu_freqs[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) 400000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) 533000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) 667000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) 800000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) 1000000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) 1067000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) 1200000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) static u32 __init a370_get_cpu_freq(void __iomem *sar)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) u32 cpu_freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) u8 cpu_freq_select = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) cpu_freq_select = ((readl(sar) >> SARL_A370_PCLK_FREQ_OPT) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) SARL_A370_PCLK_FREQ_OPT_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) if (cpu_freq_select >= ARRAY_SIZE(a370_cpu_freqs)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) pr_err("CPU freq select unsupported %d\n", cpu_freq_select);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) cpu_freq = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) } else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) cpu_freq = a370_cpu_freqs[cpu_freq_select];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) return cpu_freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) static const int a370_nbclk_ratios[32][2] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) {0, 1}, {1, 2}, {2, 2}, {2, 2},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) {1, 2}, {1, 2}, {1, 1}, {2, 3},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) {0, 1}, {1, 2}, {2, 4}, {0, 1},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) {1, 2}, {0, 1}, {0, 1}, {2, 2},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) {0, 1}, {0, 1}, {0, 1}, {1, 1},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) {2, 3}, {0, 1}, {0, 1}, {0, 1},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) {0, 1}, {0, 1}, {0, 1}, {1, 1},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) {0, 1}, {0, 1}, {0, 1}, {0, 1},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) static const int a370_hclk_ratios[32][2] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) {0, 1}, {1, 2}, {2, 6}, {2, 3},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) {1, 3}, {1, 4}, {1, 2}, {2, 6},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) {0, 1}, {1, 6}, {2, 10}, {0, 1},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) {1, 4}, {0, 1}, {0, 1}, {2, 5},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) {0, 1}, {0, 1}, {0, 1}, {1, 2},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) {2, 6}, {0, 1}, {0, 1}, {0, 1},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) {0, 1}, {0, 1}, {0, 1}, {1, 1},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) {0, 1}, {0, 1}, {0, 1}, {0, 1},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) static const int a370_dramclk_ratios[32][2] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) {0, 1}, {1, 2}, {2, 3}, {2, 3},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) {1, 3}, {1, 2}, {1, 2}, {2, 6},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) {0, 1}, {1, 3}, {2, 5}, {0, 1},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) {1, 4}, {0, 1}, {0, 1}, {2, 5},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) {0, 1}, {0, 1}, {0, 1}, {1, 1},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) {2, 3}, {0, 1}, {0, 1}, {0, 1},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) {0, 1}, {0, 1}, {0, 1}, {1, 1},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) {0, 1}, {0, 1}, {0, 1}, {0, 1},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) static void __init a370_get_clk_ratio(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) void __iomem *sar, int id, int *mult, int *div)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) u32 opt = ((readl(sar) >> SARL_A370_FAB_FREQ_OPT) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) SARL_A370_FAB_FREQ_OPT_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) switch (id) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) case A370_CPU_TO_NBCLK:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) *mult = a370_nbclk_ratios[opt][0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) *div = a370_nbclk_ratios[opt][1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) case A370_CPU_TO_HCLK:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) *mult = a370_hclk_ratios[opt][0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) *div = a370_hclk_ratios[opt][1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) case A370_CPU_TO_DRAMCLK:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) *mult = a370_dramclk_ratios[opt][0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) *div = a370_dramclk_ratios[opt][1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) static bool a370_is_sscg_enabled(void __iomem *sar)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) return !(readl(sar) & SARL_A370_SSCG_ENABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) static const struct coreclk_soc_desc a370_coreclks = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) .get_tclk_freq = a370_get_tclk_freq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) .get_cpu_freq = a370_get_cpu_freq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) .get_clk_ratio = a370_get_clk_ratio,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) .is_sscg_enabled = a370_is_sscg_enabled,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) .fix_sscg_deviation = kirkwood_fix_sscg_deviation,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) .ratios = a370_coreclk_ratios,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) .num_ratios = ARRAY_SIZE(a370_coreclk_ratios),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) * Clock Gating Control
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) static const struct clk_gating_soc_desc a370_gating_desc[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) { "audio", NULL, 0, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) { "pex0_en", NULL, 1, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) { "pex1_en", NULL, 2, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) { "ge1", NULL, 3, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) { "ge0", NULL, 4, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) { "pex0", "pex0_en", 5, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) { "pex1", "pex1_en", 9, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) { "sata0", NULL, 15, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) { "sdio", NULL, 17, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) { "crypto", NULL, 23, CLK_IGNORE_UNUSED },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) { "tdm", NULL, 25, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) { "ddr", NULL, 28, CLK_IGNORE_UNUSED },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) { "sata1", NULL, 30, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) static void __init a370_clk_init(struct device_node *np)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) struct device_node *cgnp =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) of_find_compatible_node(NULL, NULL, "marvell,armada-370-gating-clock");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) mvebu_coreclk_setup(np, &a370_coreclks);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) if (cgnp) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) mvebu_clk_gating_setup(cgnp, a370_gating_desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) of_node_put(cgnp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) CLK_OF_DECLARE(a370_clk, "marvell,armada-370-core-clock", a370_clk_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184)
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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