Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * Marvell Armada AP806 System Controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  * Copyright (C) 2016 Marvell
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)  * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #define pr_fmt(fmt) "ap806-system-controller: " fmt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #include "armada_ap_cp_helper.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #include <linux/clk-provider.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #include <linux/mfd/syscon.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) #include <linux/regmap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) #define AP806_SAR_REG			0x400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) #define AP806_SAR_CLKFREQ_MODE_MASK	0x1f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) #define AP806_CLK_NUM			6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) static struct clk *ap806_clks[AP806_CLK_NUM];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) static struct clk_onecell_data ap806_clk_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) 	.clks = ap806_clks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) 	.clk_num = AP806_CLK_NUM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) static int ap806_get_sar_clocks(unsigned int freq_mode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) 				unsigned int *cpuclk_freq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) 				unsigned int *dclk_freq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) 	switch (freq_mode) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) 	case 0x0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) 		*cpuclk_freq = 2000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) 		*dclk_freq = 600;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) 	case 0x1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) 		*cpuclk_freq = 2000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) 		*dclk_freq = 525;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) 	case 0x6:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) 		*cpuclk_freq = 1800;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) 		*dclk_freq = 600;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) 	case 0x7:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) 		*cpuclk_freq = 1800;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) 		*dclk_freq = 525;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) 	case 0x4:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) 		*cpuclk_freq = 1600;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) 		*dclk_freq = 400;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) 	case 0xB:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 		*cpuclk_freq = 1600;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) 		*dclk_freq = 450;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 	case 0xD:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 		*cpuclk_freq = 1600;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 		*dclk_freq = 525;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 	case 0x1a:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) 		*cpuclk_freq = 1400;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 		*dclk_freq = 400;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 	case 0x14:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 		*cpuclk_freq = 1300;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 		*dclk_freq = 400;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 	case 0x17:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 		*cpuclk_freq = 1300;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 		*dclk_freq = 325;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 	case 0x19:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 		*cpuclk_freq = 1200;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 		*dclk_freq = 400;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 	case 0x13:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 		*cpuclk_freq = 1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 		*dclk_freq = 325;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 	case 0x1d:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 		*cpuclk_freq = 1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 		*dclk_freq = 400;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 	case 0x1c:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 		*cpuclk_freq = 800;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 		*dclk_freq = 400;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 	case 0x1b:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 		*cpuclk_freq = 600;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 		*dclk_freq = 400;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 	default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) static int ap807_get_sar_clocks(unsigned int freq_mode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 				unsigned int *cpuclk_freq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 				unsigned int *dclk_freq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 	switch (freq_mode) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 	case 0x0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 		*cpuclk_freq = 2000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 		*dclk_freq = 1200;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 	case 0x6:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 		*cpuclk_freq = 2200;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 		*dclk_freq = 1200;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 	case 0xD:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 		*cpuclk_freq = 1600;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 		*dclk_freq = 1200;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 	default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) static int ap806_syscon_common_probe(struct platform_device *pdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 				     struct device_node *syscon_node)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 	unsigned int freq_mode, cpuclk_freq, dclk_freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 	const char *name, *fixedclk_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 	struct device *dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 	struct device_node *np = dev->of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 	struct regmap *regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 	u32 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 	regmap = syscon_node_to_regmap(syscon_node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 	if (IS_ERR(regmap)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 		dev_err(dev, "cannot get regmap\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 		return PTR_ERR(regmap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 	ret = regmap_read(regmap, AP806_SAR_REG, &reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 	if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 		dev_err(dev, "cannot read from regmap\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 	freq_mode = reg & AP806_SAR_CLKFREQ_MODE_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 	if (of_device_is_compatible(pdev->dev.of_node,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 				    "marvell,ap806-clock")) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 		ret = ap806_get_sar_clocks(freq_mode, &cpuclk_freq, &dclk_freq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 	} else if (of_device_is_compatible(pdev->dev.of_node,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 					   "marvell,ap807-clock")) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 		ret = ap807_get_sar_clocks(freq_mode, &cpuclk_freq, &dclk_freq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 	} else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 		dev_err(dev, "compatible not supported\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 	if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 		dev_err(dev, "invalid Sample at Reset value\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 	/* Convert to hertz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 	cpuclk_freq *= 1000 * 1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 	dclk_freq *= 1000 * 1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 	/* CPU clocks depend on the Sample At Reset configuration */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 	name = ap_cp_unique_name(dev, syscon_node, "pll-cluster-0");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 	ap806_clks[0] = clk_register_fixed_rate(dev, name, NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 						0, cpuclk_freq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 	if (IS_ERR(ap806_clks[0])) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 		ret = PTR_ERR(ap806_clks[0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 		goto fail0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 	name = ap_cp_unique_name(dev, syscon_node, "pll-cluster-1");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 	ap806_clks[1] = clk_register_fixed_rate(dev, name, NULL, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 						cpuclk_freq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 	if (IS_ERR(ap806_clks[1])) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 		ret = PTR_ERR(ap806_clks[1]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 		goto fail1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 	/* Fixed clock is always 1200 Mhz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 	fixedclk_name = ap_cp_unique_name(dev, syscon_node, "fixed");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 	ap806_clks[2] = clk_register_fixed_rate(dev, fixedclk_name, NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 						0, 1200 * 1000 * 1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 	if (IS_ERR(ap806_clks[2])) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 		ret = PTR_ERR(ap806_clks[2]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 		goto fail2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 	/* MSS Clock is fixed clock divided by 6 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 	name = ap_cp_unique_name(dev, syscon_node, "mss");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 	ap806_clks[3] = clk_register_fixed_factor(NULL, name, fixedclk_name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 						  0, 1, 6);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 	if (IS_ERR(ap806_clks[3])) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 		ret = PTR_ERR(ap806_clks[3]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 		goto fail3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 	/* SDIO(/eMMC) Clock is fixed clock divided by 3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 	name = ap_cp_unique_name(dev, syscon_node, "sdio");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 	ap806_clks[4] = clk_register_fixed_factor(NULL, name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 						  fixedclk_name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 						  0, 1, 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 	if (IS_ERR(ap806_clks[4])) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 		ret = PTR_ERR(ap806_clks[4]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 		goto fail4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 	/* AP-DCLK(HCLK) Clock is DDR clock divided by 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 	name = ap_cp_unique_name(dev, syscon_node, "ap-dclk");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 	ap806_clks[5] = clk_register_fixed_rate(dev, name, NULL, 0, dclk_freq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 	if (IS_ERR(ap806_clks[5])) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 		ret = PTR_ERR(ap806_clks[5]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 		goto fail5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 	ret = of_clk_add_provider(np, of_clk_src_onecell_get, &ap806_clk_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 		goto fail_clk_add;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) fail_clk_add:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 	clk_unregister_fixed_factor(ap806_clks[5]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) fail5:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 	clk_unregister_fixed_factor(ap806_clks[4]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) fail4:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 	clk_unregister_fixed_factor(ap806_clks[3]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) fail3:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 	clk_unregister_fixed_rate(ap806_clks[2]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) fail2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 	clk_unregister_fixed_rate(ap806_clks[1]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) fail1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 	clk_unregister_fixed_rate(ap806_clks[0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) fail0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 	return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) static int ap806_syscon_legacy_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 	dev_warn(&pdev->dev, FW_WARN "Using legacy device tree binding\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 	dev_warn(&pdev->dev, FW_WARN "Update your device tree:\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) 	dev_warn(&pdev->dev, FW_WARN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 		 "This binding won't be supported in future kernel\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) 	return ap806_syscon_common_probe(pdev, pdev->dev.of_node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) static int ap806_clock_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) 	return ap806_syscon_common_probe(pdev, pdev->dev.of_node->parent);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) static const struct of_device_id ap806_syscon_legacy_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) 	{ .compatible = "marvell,ap806-system-controller", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) 	{ }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) static struct platform_driver ap806_syscon_legacy_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) 	.probe = ap806_syscon_legacy_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) 	.driver		= {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) 		.name	= "marvell-ap806-system-controller",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) 		.of_match_table = ap806_syscon_legacy_of_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) 		.suppress_bind_attrs = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) builtin_platform_driver(ap806_syscon_legacy_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) static const struct of_device_id ap806_clock_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) 	{ .compatible = "marvell,ap806-clock", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) 	{ .compatible = "marvell,ap807-clock", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) 	{ }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) static struct platform_driver ap806_clock_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) 	.probe = ap806_clock_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) 	.driver		= {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) 		.name	= "marvell-ap806-clock",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) 		.of_match_table = ap806_clock_of_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) 		.suppress_bind_attrs = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) builtin_platform_driver(ap806_clock_driver);