Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * Marvell Armada AP CPU Clock Controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  * Copyright (C) 2018 Marvell
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)  * Omri Itach <omrii@marvell.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8)  * Gregory Clement <gregory.clement@bootlin.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #define pr_fmt(fmt) "ap-cpu-clk: " fmt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #include <linux/clk-provider.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #include <linux/mfd/syscon.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #include <linux/of_address.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #include <linux/of_platform.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) #include <linux/regmap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) #include "armada_ap_cp_helper.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) #define AP806_CPU_CLUSTER0		0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) #define AP806_CPU_CLUSTER1		1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) #define AP806_CPUS_PER_CLUSTER		2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) #define APN806_CPU1_MASK		0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) #define APN806_CLUSTER_NUM_OFFSET	8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) #define APN806_CLUSTER_NUM_MASK		BIT(APN806_CLUSTER_NUM_OFFSET)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) #define APN806_MAX_DIVIDER		32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34)  * struct cpu_dfs_regs: CPU DFS register mapping
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35)  * @divider_reg: full integer ratio from PLL frequency to CPU clock frequency
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36)  * @force_reg: request to force new ratio regardless of relation to other clocks
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37)  * @ratio_reg: central request to switch ratios
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) struct cpu_dfs_regs {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) 	unsigned int divider_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) 	unsigned int force_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) 	unsigned int ratio_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) 	unsigned int ratio_state_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) 	unsigned int divider_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) 	unsigned int cluster_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) 	unsigned int force_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) 	int divider_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) 	int divider_ratio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) 	int ratio_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) 	int ratio_state_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) 	int ratio_state_cluster_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) /* AP806 CPU DFS register mapping*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) #define AP806_CA72MP2_0_PLL_CR_0_REG_OFFSET		0x278
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) #define AP806_CA72MP2_0_PLL_CR_1_REG_OFFSET		0x280
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) #define AP806_CA72MP2_0_PLL_CR_2_REG_OFFSET		0x284
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) #define AP806_CA72MP2_0_PLL_SR_REG_OFFSET		0xC94
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) #define AP806_CA72MP2_0_PLL_CR_CLUSTER_OFFSET		0x14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) #define AP806_PLL_CR_0_CPU_CLK_DIV_RATIO_OFFSET		0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) #define AP806_PLL_CR_CPU_CLK_DIV_RATIO			0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) #define AP806_PLL_CR_0_CPU_CLK_DIV_RATIO_MASK \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 			(0x3f << AP806_PLL_CR_0_CPU_CLK_DIV_RATIO_OFFSET)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) #define AP806_PLL_CR_0_CPU_CLK_RELOAD_FORCE_OFFSET	24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) #define AP806_PLL_CR_0_CPU_CLK_RELOAD_FORCE_MASK \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) 			(0x1 << AP806_PLL_CR_0_CPU_CLK_RELOAD_FORCE_OFFSET)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) #define AP806_PLL_CR_0_CPU_CLK_RELOAD_RATIO_OFFSET	16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) #define AP806_CA72MP2_0_PLL_RATIO_STABLE_OFFSET	0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) #define AP806_CA72MP2_0_PLL_RATIO_STATE			11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) #define STATUS_POLL_PERIOD_US		1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) #define STATUS_POLL_TIMEOUT_US		1000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) #define to_ap_cpu_clk(_hw) container_of(_hw, struct ap_cpu_clk, hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) static const struct cpu_dfs_regs ap806_dfs_regs = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 	.divider_reg = AP806_CA72MP2_0_PLL_CR_0_REG_OFFSET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 	.force_reg = AP806_CA72MP2_0_PLL_CR_1_REG_OFFSET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 	.ratio_reg = AP806_CA72MP2_0_PLL_CR_2_REG_OFFSET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 	.ratio_state_reg = AP806_CA72MP2_0_PLL_SR_REG_OFFSET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 	.divider_mask = AP806_PLL_CR_0_CPU_CLK_DIV_RATIO_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 	.cluster_offset = AP806_CA72MP2_0_PLL_CR_CLUSTER_OFFSET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 	.force_mask = AP806_PLL_CR_0_CPU_CLK_RELOAD_FORCE_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 	.divider_offset = AP806_PLL_CR_0_CPU_CLK_DIV_RATIO_OFFSET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 	.divider_ratio = AP806_PLL_CR_CPU_CLK_DIV_RATIO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 	.ratio_offset = AP806_PLL_CR_0_CPU_CLK_RELOAD_RATIO_OFFSET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 	.ratio_state_offset = AP806_CA72MP2_0_PLL_RATIO_STABLE_OFFSET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 	.ratio_state_cluster_offset = AP806_CA72MP2_0_PLL_RATIO_STABLE_OFFSET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) /* AP807 CPU DFS register mapping */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) #define AP807_DEVICE_GENERAL_CONTROL_10_REG_OFFSET		0x278
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) #define AP807_DEVICE_GENERAL_CONTROL_11_REG_OFFSET		0x27c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) #define AP807_DEVICE_GENERAL_STATUS_6_REG_OFFSET		0xc98
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) #define AP807_CA72MP2_0_PLL_CR_CLUSTER_OFFSET			0x8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) #define AP807_PLL_CR_0_CPU_CLK_DIV_RATIO_OFFSET			18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) #define AP807_PLL_CR_0_CPU_CLK_DIV_RATIO_MASK \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 		(0x3f << AP807_PLL_CR_0_CPU_CLK_DIV_RATIO_OFFSET)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define AP807_PLL_CR_1_CPU_CLK_DIV_RATIO_OFFSET			12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define AP807_PLL_CR_1_CPU_CLK_DIV_RATIO_MASK \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 		(0x3f << AP807_PLL_CR_1_CPU_CLK_DIV_RATIO_OFFSET)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define AP807_PLL_CR_CPU_CLK_DIV_RATIO				3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define AP807_PLL_CR_0_CPU_CLK_RELOAD_FORCE_OFFSET		0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define AP807_PLL_CR_0_CPU_CLK_RELOAD_FORCE_MASK \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 		(0x3 << AP807_PLL_CR_0_CPU_CLK_RELOAD_FORCE_OFFSET)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define AP807_PLL_CR_0_CPU_CLK_RELOAD_RATIO_OFFSET		6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define	AP807_CA72MP2_0_PLL_CLKDIV_RATIO_STABLE_OFFSET		20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define AP807_CA72MP2_0_PLL_CLKDIV_RATIO_STABLE_CLUSTER_OFFSET	3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) static const struct cpu_dfs_regs ap807_dfs_regs = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 	.divider_reg = AP807_DEVICE_GENERAL_CONTROL_10_REG_OFFSET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 	.force_reg = AP807_DEVICE_GENERAL_CONTROL_11_REG_OFFSET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 	.ratio_reg = AP807_DEVICE_GENERAL_CONTROL_11_REG_OFFSET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 	.ratio_state_reg = AP807_DEVICE_GENERAL_STATUS_6_REG_OFFSET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 	.divider_mask = AP807_PLL_CR_0_CPU_CLK_DIV_RATIO_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 	.cluster_offset = AP807_CA72MP2_0_PLL_CR_CLUSTER_OFFSET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 	.force_mask = AP807_PLL_CR_0_CPU_CLK_RELOAD_FORCE_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 	.divider_offset = AP807_PLL_CR_0_CPU_CLK_DIV_RATIO_OFFSET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 	.divider_ratio = AP807_PLL_CR_CPU_CLK_DIV_RATIO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 	.ratio_offset = AP807_PLL_CR_0_CPU_CLK_RELOAD_RATIO_OFFSET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 	.ratio_state_offset = AP807_CA72MP2_0_PLL_CLKDIV_RATIO_STABLE_OFFSET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 	.ratio_state_cluster_offset =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 		AP807_CA72MP2_0_PLL_CLKDIV_RATIO_STABLE_CLUSTER_OFFSET
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128)  * struct ap806_clk: CPU cluster clock controller instance
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129)  * @cluster: Cluster clock controller index
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130)  * @clk_name: Cluster clock controller name
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131)  * @dev : Cluster clock device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132)  * @hw: HW specific structure of Cluster clock controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133)  * @pll_cr_base: CA72MP2 Register base (Device Sample at Reset register)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) struct ap_cpu_clk {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 	unsigned int cluster;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 	const char *clk_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 	struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 	struct clk_hw hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 	struct regmap *pll_cr_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 	const struct cpu_dfs_regs *pll_regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) static unsigned long ap_cpu_clk_recalc_rate(struct clk_hw *hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 					    unsigned long parent_rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 	struct ap_cpu_clk *clk = to_ap_cpu_clk(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 	unsigned int cpu_clkdiv_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 	int cpu_clkdiv_ratio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 	cpu_clkdiv_reg = clk->pll_regs->divider_reg +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 		(clk->cluster * clk->pll_regs->cluster_offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 	regmap_read(clk->pll_cr_base, cpu_clkdiv_reg, &cpu_clkdiv_ratio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 	cpu_clkdiv_ratio &= clk->pll_regs->divider_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 	cpu_clkdiv_ratio >>= clk->pll_regs->divider_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 	return parent_rate / cpu_clkdiv_ratio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) static int ap_cpu_clk_set_rate(struct clk_hw *hw, unsigned long rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 			       unsigned long parent_rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 	struct ap_cpu_clk *clk = to_ap_cpu_clk(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 	int ret, reg, divider = parent_rate / rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 	unsigned int cpu_clkdiv_reg, cpu_force_reg, cpu_ratio_reg, stable_bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 	cpu_clkdiv_reg = clk->pll_regs->divider_reg +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 		(clk->cluster * clk->pll_regs->cluster_offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 	cpu_force_reg = clk->pll_regs->force_reg +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 		(clk->cluster * clk->pll_regs->cluster_offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 	cpu_ratio_reg = clk->pll_regs->ratio_reg +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 		(clk->cluster * clk->pll_regs->cluster_offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 	regmap_read(clk->pll_cr_base, cpu_clkdiv_reg, &reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 	reg &= ~(clk->pll_regs->divider_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 	reg |= (divider << clk->pll_regs->divider_offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 	 * AP807 CPU divider has two channels with ratio 1:3 and divider_ratio
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 	 * is 1. Otherwise, in the case of the AP806, divider_ratio is 0.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 	if (clk->pll_regs->divider_ratio) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 		reg &= ~(AP807_PLL_CR_1_CPU_CLK_DIV_RATIO_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 		reg |= ((divider * clk->pll_regs->divider_ratio) <<
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 				AP807_PLL_CR_1_CPU_CLK_DIV_RATIO_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 	regmap_write(clk->pll_cr_base, cpu_clkdiv_reg, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 	regmap_update_bits(clk->pll_cr_base, cpu_force_reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 			   clk->pll_regs->force_mask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 			   clk->pll_regs->force_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 	regmap_update_bits(clk->pll_cr_base, cpu_ratio_reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 			   BIT(clk->pll_regs->ratio_offset),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 			   BIT(clk->pll_regs->ratio_offset));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 	stable_bit = BIT(clk->pll_regs->ratio_state_offset +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 			 clk->cluster *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 			 clk->pll_regs->ratio_state_cluster_offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 	ret = regmap_read_poll_timeout(clk->pll_cr_base,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 				       clk->pll_regs->ratio_state_reg, reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 				       reg & stable_bit, STATUS_POLL_PERIOD_US,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 				       STATUS_POLL_TIMEOUT_US);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 	regmap_update_bits(clk->pll_cr_base, cpu_ratio_reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 			   BIT(clk->pll_regs->ratio_offset), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) static long ap_cpu_clk_round_rate(struct clk_hw *hw, unsigned long rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 				  unsigned long *parent_rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 	int divider = *parent_rate / rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 	divider = min(divider, APN806_MAX_DIVIDER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 	return *parent_rate / divider;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) static const struct clk_ops ap_cpu_clk_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 	.recalc_rate	= ap_cpu_clk_recalc_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 	.round_rate	= ap_cpu_clk_round_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 	.set_rate	= ap_cpu_clk_set_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) static int ap_cpu_clock_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 	int ret, nclusters = 0, cluster_index = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 	struct device *dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 	struct device_node *dn, *np = dev->of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 	struct clk_hw_onecell_data *ap_cpu_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 	struct ap_cpu_clk *ap_cpu_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 	struct regmap *regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 	regmap = syscon_node_to_regmap(np->parent);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 	if (IS_ERR(regmap)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 		pr_err("cannot get pll_cr_base regmap\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 		return PTR_ERR(regmap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 	 * AP806 has 4 cpus and DFS for AP806 is controlled per
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 	 * cluster (2 CPUs per cluster), cpu0 and cpu1 are fixed to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 	 * cluster0 while cpu2 and cpu3 are fixed to cluster1 whether
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 	 * they are enabled or not.  Since cpu0 is the boot cpu, then
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 	 * cluster0 must exist.  If cpu2 or cpu3 is enabled, cluster1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 	 * will exist and the cluster number is 2; otherwise the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 	 * cluster number is 1.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 	nclusters = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) 	for_each_of_cpu_node(dn) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) 		int cpu, err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) 		err = of_property_read_u32(dn, "reg", &cpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) 		if (WARN_ON(err)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) 			of_node_put(dn);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) 			return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) 		/* If cpu2 or cpu3 is enabled */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) 		if (cpu & APN806_CLUSTER_NUM_MASK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) 			nclusters = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) 			of_node_put(dn);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) 			break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) 	 * DFS for AP806 is controlled per cluster (2 CPUs per cluster),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) 	 * so allocate structs per cluster
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) 	ap_cpu_clk = devm_kcalloc(dev, nclusters, sizeof(*ap_cpu_clk),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) 				  GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) 	if (!ap_cpu_clk)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) 		return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) 	ap_cpu_data = devm_kzalloc(dev, struct_size(ap_cpu_data, hws,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) 						    nclusters),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) 				GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) 	if (!ap_cpu_data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) 		return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) 	for_each_of_cpu_node(dn) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) 		char *clk_name = "cpu-cluster-0";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) 		struct clk_init_data init;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) 		const char *parent_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) 		struct clk *parent;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) 		int cpu, err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) 		err = of_property_read_u32(dn, "reg", &cpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) 		if (WARN_ON(err)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) 			of_node_put(dn);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) 			return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) 		cluster_index = cpu & APN806_CLUSTER_NUM_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) 		cluster_index >>= APN806_CLUSTER_NUM_OFFSET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) 		/* Initialize once for one cluster */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) 		if (ap_cpu_data->hws[cluster_index])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) 			continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) 		parent = of_clk_get(np, cluster_index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) 		if (IS_ERR(parent)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) 			dev_err(dev, "Could not get the clock parent\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) 			of_node_put(dn);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) 			return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) 		parent_name =  __clk_get_name(parent);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) 		clk_name[12] += cluster_index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) 		ap_cpu_clk[cluster_index].clk_name =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) 			ap_cp_unique_name(dev, np->parent, clk_name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) 		ap_cpu_clk[cluster_index].cluster = cluster_index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) 		ap_cpu_clk[cluster_index].pll_cr_base = regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) 		ap_cpu_clk[cluster_index].hw.init = &init;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) 		ap_cpu_clk[cluster_index].dev = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) 		ap_cpu_clk[cluster_index].pll_regs = of_device_get_match_data(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) 		init.name = ap_cpu_clk[cluster_index].clk_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) 		init.ops = &ap_cpu_clk_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) 		init.num_parents = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) 		init.parent_names = &parent_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) 		ret = devm_clk_hw_register(dev, &ap_cpu_clk[cluster_index].hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) 		if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) 			of_node_put(dn);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) 			return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) 		ap_cpu_data->hws[cluster_index] = &ap_cpu_clk[cluster_index].hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) 	ap_cpu_data->num = cluster_index + 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) 	ret = of_clk_add_hw_provider(np, of_clk_hw_onecell_get, ap_cpu_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) 		dev_err(dev, "failed to register OF clock provider\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) 	return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) static const struct of_device_id ap_cpu_clock_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) 	{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) 		.compatible = "marvell,ap806-cpu-clock",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) 		.data = &ap806_dfs_regs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) 	{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) 		.compatible = "marvell,ap807-cpu-clock",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) 		.data = &ap807_dfs_regs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) 	{ }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) static struct platform_driver ap_cpu_clock_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) 	.probe = ap_cpu_clock_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) 	.driver		= {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) 		.name	= "marvell-ap-cpu-clock",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) 		.of_match_table = ap_cpu_clock_of_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) 		.suppress_bind_attrs = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) builtin_platform_driver(ap_cpu_clock_driver);