Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5) #include <linux/of_address.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6) #include <linux/reset-controller.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8) #include "reset.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) #define rcdev_to_unit(rcdev) container_of(rcdev, struct mmp_clk_reset_unit, rcdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) static int mmp_of_reset_xlate(struct reset_controller_dev *rcdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) 			  const struct of_phandle_args *reset_spec)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) 	struct mmp_clk_reset_unit *unit = rcdev_to_unit(rcdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) 	struct mmp_clk_reset_cell *cell;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) 	int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) 	if (WARN_ON(reset_spec->args_count != rcdev->of_reset_n_cells))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) 	for (i = 0; i < rcdev->nr_resets; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) 		cell = &unit->cells[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) 		if (cell->clk_id == reset_spec->args[0])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) 			break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) 	if (i == rcdev->nr_resets)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) 	return i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) static int mmp_clk_reset_assert(struct reset_controller_dev *rcdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) 				unsigned long id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) 	struct mmp_clk_reset_unit *unit = rcdev_to_unit(rcdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) 	struct mmp_clk_reset_cell *cell;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) 	unsigned long flags = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) 	u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) 	cell = &unit->cells[id];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) 	if (cell->lock)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) 		spin_lock_irqsave(cell->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) 	val = readl(cell->reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) 	val |= cell->bits;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) 	writel(val, cell->reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) 	if (cell->lock)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) 		spin_unlock_irqrestore(cell->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) static int mmp_clk_reset_deassert(struct reset_controller_dev *rcdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) 				unsigned long id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 	struct mmp_clk_reset_unit *unit = rcdev_to_unit(rcdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) 	struct mmp_clk_reset_cell *cell;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 	unsigned long flags = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 	u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 	cell = &unit->cells[id];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 	if (cell->lock)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 		spin_lock_irqsave(cell->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 	val = readl(cell->reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 	val &= ~cell->bits;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 	writel(val, cell->reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 	if (cell->lock)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 		spin_unlock_irqrestore(cell->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) static const struct reset_control_ops mmp_clk_reset_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 	.assert		= mmp_clk_reset_assert,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 	.deassert	= mmp_clk_reset_deassert,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) void mmp_clk_reset_register(struct device_node *np,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 			struct mmp_clk_reset_cell *cells, int nr_resets)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 	struct mmp_clk_reset_unit *unit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 	unit = kzalloc(sizeof(*unit), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 	if (!unit)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 		return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 	unit->cells = cells;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 	unit->rcdev.of_reset_n_cells = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 	unit->rcdev.nr_resets = nr_resets;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 	unit->rcdev.ops = &mmp_clk_reset_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 	unit->rcdev.of_node = np;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 	unit->rcdev.of_xlate = mmp_of_reset_xlate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 	reset_controller_register(&unit->rcdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) }