^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) #ifndef __MACH_MMP_CLK_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) #define __MACH_MMP_CLK_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) #include <linux/clk-provider.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) #include <linux/pm_domain.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include <linux/clkdev.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #define APBC_NO_BUS_CTRL BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #define APBC_POWER_CTRL BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) /* Clock type "factor" */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) struct mmp_clk_factor_masks {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) unsigned int factor;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) unsigned int num_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) unsigned int den_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) unsigned int num_shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) unsigned int den_shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) unsigned int enable_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) struct mmp_clk_factor_tbl {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) unsigned int num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) unsigned int den;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) struct mmp_clk_factor {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) struct clk_hw hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) struct mmp_clk_factor_masks *masks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) struct mmp_clk_factor_tbl *ftbl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) unsigned int ftbl_cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) spinlock_t *lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) extern struct clk *mmp_clk_register_factor(const char *name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) const char *parent_name, unsigned long flags,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) void __iomem *base, struct mmp_clk_factor_masks *masks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) struct mmp_clk_factor_tbl *ftbl, unsigned int ftbl_cnt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) spinlock_t *lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) /* Clock type "mix" */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define MMP_CLK_BITS_MASK(width, shift) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) (((1 << (width)) - 1) << (shift))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define MMP_CLK_BITS_GET_VAL(data, width, shift) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) ((data & MMP_CLK_BITS_MASK(width, shift)) >> (shift))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define MMP_CLK_BITS_SET_VAL(val, width, shift) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) (((val) << (shift)) & MMP_CLK_BITS_MASK(width, shift))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) MMP_CLK_MIX_TYPE_V1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) MMP_CLK_MIX_TYPE_V2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) MMP_CLK_MIX_TYPE_V3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) /* The register layout */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) struct mmp_clk_mix_reg_info {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) void __iomem *reg_clk_ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) void __iomem *reg_clk_sel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) u8 width_div;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) u8 shift_div;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) u8 width_mux;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) u8 shift_mux;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) u8 bit_fc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) /* The suggested clock table from user. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) struct mmp_clk_mix_clk_table {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) unsigned long rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) u8 parent_index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) unsigned int divisor;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) unsigned int valid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) struct mmp_clk_mix_config {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) struct mmp_clk_mix_reg_info reg_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) struct mmp_clk_mix_clk_table *table;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) unsigned int table_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) u32 *mux_table;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) struct clk_div_table *div_table;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) u8 div_flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) u8 mux_flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) struct mmp_clk_mix {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) struct clk_hw hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) struct mmp_clk_mix_reg_info reg_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) struct mmp_clk_mix_clk_table *table;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) u32 *mux_table;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) struct clk_div_table *div_table;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) unsigned int table_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) u8 div_flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) u8 mux_flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) unsigned int type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) spinlock_t *lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) extern const struct clk_ops mmp_clk_mix_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) extern struct clk *mmp_clk_register_mix(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) const char *name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) const char * const *parent_names,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) u8 num_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) unsigned long flags,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) struct mmp_clk_mix_config *config,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) spinlock_t *lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) /* Clock type "gate". MMP private gate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define MMP_CLK_GATE_NEED_DELAY BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) struct mmp_clk_gate {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) struct clk_hw hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) void __iomem *reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) u32 mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) u32 val_enable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) u32 val_disable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) unsigned int flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) spinlock_t *lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) extern const struct clk_ops mmp_clk_gate_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) extern struct clk *mmp_clk_register_gate(struct device *dev, const char *name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) const char *parent_name, unsigned long flags,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) void __iomem *reg, u32 mask, u32 val_enable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) u32 val_disable, unsigned int gate_flags,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) spinlock_t *lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) extern struct clk *mmp_clk_register_apbc(const char *name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) const char *parent_name, void __iomem *base,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) unsigned int delay, unsigned int apbc_flags, spinlock_t *lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) extern struct clk *mmp_clk_register_apmu(const char *name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) const char *parent_name, void __iomem *base, u32 enable_mask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) spinlock_t *lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) struct mmp_clk_unit {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) unsigned int nr_clks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) struct clk **clk_table;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) struct clk_onecell_data clk_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) struct mmp_param_fixed_rate_clk {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) unsigned int id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) char *name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) const char *parent_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) unsigned long fixed_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) void mmp_register_fixed_rate_clks(struct mmp_clk_unit *unit,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) struct mmp_param_fixed_rate_clk *clks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) int size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) struct mmp_param_fixed_factor_clk {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) unsigned int id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) char *name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) const char *parent_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) unsigned long mult;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) unsigned long div;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) void mmp_register_fixed_factor_clks(struct mmp_clk_unit *unit,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) struct mmp_param_fixed_factor_clk *clks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) int size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) struct mmp_param_general_gate_clk {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) unsigned int id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) const char *name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) const char *parent_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) unsigned long offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) u8 bit_idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) u8 gate_flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) spinlock_t *lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) void mmp_register_general_gate_clks(struct mmp_clk_unit *unit,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) struct mmp_param_general_gate_clk *clks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) void __iomem *base, int size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) struct mmp_param_gate_clk {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) unsigned int id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) char *name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) const char *parent_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) unsigned long offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) u32 mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) u32 val_enable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) u32 val_disable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) unsigned int gate_flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) spinlock_t *lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) void mmp_register_gate_clks(struct mmp_clk_unit *unit,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) struct mmp_param_gate_clk *clks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) void __iomem *base, int size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) struct mmp_param_mux_clk {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) unsigned int id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) char *name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) const char * const *parent_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) u8 num_parents;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) unsigned long offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) u8 shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) u8 width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) u8 mux_flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) spinlock_t *lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) void mmp_register_mux_clks(struct mmp_clk_unit *unit,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) struct mmp_param_mux_clk *clks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) void __iomem *base, int size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) struct mmp_param_div_clk {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) unsigned int id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) char *name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) const char *parent_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) unsigned long offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) u8 shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) u8 width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) u8 div_flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) spinlock_t *lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) void mmp_register_div_clks(struct mmp_clk_unit *unit,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) struct mmp_param_div_clk *clks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) void __iomem *base, int size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) struct mmp_param_pll_clk {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) unsigned int id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) char *name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) unsigned long default_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) unsigned long enable_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) u32 enable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) unsigned long offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) u8 shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) /* MMP3 specific: */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) unsigned long input_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) unsigned long postdiv_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) unsigned long postdiv_shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) void mmp_register_pll_clks(struct mmp_clk_unit *unit,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) struct mmp_param_pll_clk *clks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) void __iomem *base, int size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) #define DEFINE_MIX_REG_INFO(w_d, s_d, w_m, s_m, fc) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) .width_div = (w_d), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) .shift_div = (s_d), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) .width_mux = (w_m), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) .shift_mux = (s_m), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) .bit_fc = (fc), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) void mmp_clk_init(struct device_node *np, struct mmp_clk_unit *unit,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) int nr_clks);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) void mmp_clk_add(struct mmp_clk_unit *unit, unsigned int id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) struct clk *clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) /* Power islands */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) #define MMP_PM_DOMAIN_NO_DISABLE BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) struct generic_pm_domain *mmp_pm_domain_register(const char *name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) void __iomem *reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) u32 power_on, u32 reset, u32 clock_enable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) unsigned int flags, spinlock_t *lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) #endif
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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