^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) #include <linux/clk-provider.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) #include <linux/of_address.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include "clk.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) void mmp_clk_init(struct device_node *np, struct mmp_clk_unit *unit,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) int nr_clks)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) struct clk **clk_table;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) clk_table = kcalloc(nr_clks, sizeof(struct clk *), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) if (!clk_table)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) unit->clk_table = clk_table;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) unit->nr_clks = nr_clks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) unit->clk_data.clks = clk_table;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) unit->clk_data.clk_num = nr_clks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) of_clk_add_provider(np, of_clk_src_onecell_get, &unit->clk_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) void mmp_register_fixed_rate_clks(struct mmp_clk_unit *unit,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) struct mmp_param_fixed_rate_clk *clks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) int size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) for (i = 0; i < size; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) clk = clk_register_fixed_rate(NULL, clks[i].name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) clks[i].parent_name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) clks[i].flags,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) clks[i].fixed_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) if (IS_ERR(clk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) pr_err("%s: failed to register clock %s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) __func__, clks[i].name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) if (clks[i].id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) unit->clk_table[clks[i].id] = clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) void mmp_register_fixed_factor_clks(struct mmp_clk_unit *unit,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) struct mmp_param_fixed_factor_clk *clks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) int size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) for (i = 0; i < size; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) clk = clk_register_fixed_factor(NULL, clks[i].name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) clks[i].parent_name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) clks[i].flags, clks[i].mult,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) clks[i].div);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) if (IS_ERR(clk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) pr_err("%s: failed to register clock %s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) __func__, clks[i].name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) if (clks[i].id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) unit->clk_table[clks[i].id] = clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) void mmp_register_general_gate_clks(struct mmp_clk_unit *unit,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) struct mmp_param_general_gate_clk *clks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) void __iomem *base, int size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) for (i = 0; i < size; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) clk = clk_register_gate(NULL, clks[i].name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) clks[i].parent_name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) clks[i].flags,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) base + clks[i].offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) clks[i].bit_idx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) clks[i].gate_flags,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) clks[i].lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) if (IS_ERR(clk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) pr_err("%s: failed to register clock %s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) __func__, clks[i].name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) if (clks[i].id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) unit->clk_table[clks[i].id] = clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) void mmp_register_gate_clks(struct mmp_clk_unit *unit,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) struct mmp_param_gate_clk *clks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) void __iomem *base, int size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) for (i = 0; i < size; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) clk = mmp_clk_register_gate(NULL, clks[i].name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) clks[i].parent_name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) clks[i].flags,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) base + clks[i].offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) clks[i].mask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) clks[i].val_enable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) clks[i].val_disable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) clks[i].gate_flags,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) clks[i].lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) if (IS_ERR(clk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) pr_err("%s: failed to register clock %s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) __func__, clks[i].name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) if (clks[i].id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) unit->clk_table[clks[i].id] = clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) void mmp_register_mux_clks(struct mmp_clk_unit *unit,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) struct mmp_param_mux_clk *clks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) void __iomem *base, int size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) for (i = 0; i < size; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) clk = clk_register_mux(NULL, clks[i].name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) clks[i].parent_name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) clks[i].num_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) clks[i].flags,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) base + clks[i].offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) clks[i].shift,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) clks[i].width,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) clks[i].mux_flags,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) clks[i].lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) if (IS_ERR(clk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) pr_err("%s: failed to register clock %s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) __func__, clks[i].name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) if (clks[i].id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) unit->clk_table[clks[i].id] = clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) void mmp_register_div_clks(struct mmp_clk_unit *unit,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) struct mmp_param_div_clk *clks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) void __iomem *base, int size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) for (i = 0; i < size; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) clk = clk_register_divider(NULL, clks[i].name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) clks[i].parent_name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) clks[i].flags,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) base + clks[i].offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) clks[i].shift,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) clks[i].width,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) clks[i].div_flags,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) clks[i].lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) if (IS_ERR(clk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) pr_err("%s: failed to register clock %s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) __func__, clks[i].name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) if (clks[i].id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) unit->clk_table[clks[i].id] = clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) void mmp_clk_add(struct mmp_clk_unit *unit, unsigned int id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) struct clk *clk)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) if (IS_ERR_OR_NULL(clk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) pr_err("CLK %d has invalid pointer %p\n", id, clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) if (id >= unit->nr_clks) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) pr_err("CLK %d is invalid\n", id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) unit->clk_table[id] = clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) }
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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