^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) * pxa910 clock framework source file
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Copyright (C) 2012 Marvell
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Chao Xie <xiechao.mail@gmail.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * This file is licensed under the terms of the GNU General Public
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * License version 2. This program is licensed "as is" without any
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * warranty of any kind, whether express or implied.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/clk/mmp.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/spinlock.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include "clk.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define APBC_RTC 0x28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define APBC_TWSI0 0x2c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define APBC_KPC 0x18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define APBC_UART0 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define APBC_UART1 0x4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define APBC_GPIO 0x8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define APBC_PWM0 0xc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define APBC_PWM1 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define APBC_PWM2 0x14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define APBC_PWM3 0x18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define APBC_SSP0 0x1c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define APBC_SSP1 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define APBC_SSP2 0x4c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define APBCP_TWSI1 0x28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define APBCP_UART2 0x1c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define APMU_SDH0 0x54
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define APMU_SDH1 0x58
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define APMU_USB 0x5c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define APMU_DISP0 0x4c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define APMU_CCIC0 0x50
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define APMU_DFC 0x60
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define MPMU_UART_PLL 0x14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) static DEFINE_SPINLOCK(clk_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) static struct mmp_clk_factor_masks uart_factor_masks = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) .factor = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) .num_mask = 0x1fff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) .den_mask = 0x1fff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) .num_shift = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) .den_shift = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) static struct mmp_clk_factor_tbl uart_factor_tbl[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) {.num = 8125, .den = 1536}, /*14.745MHZ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) static const char *uart_parent[] = {"pll1_3_16", "uart_pll"};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) static const char *ssp_parent[] = {"pll1_96", "pll1_48", "pll1_24", "pll1_12"};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) static const char *sdh_parent[] = {"pll1_12", "pll1_13"};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) static const char *disp_parent[] = {"pll1_2", "pll1_12"};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) static const char *ccic_parent[] = {"pll1_2", "pll1_12"};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) static const char *ccic_phy_parent[] = {"pll1_6", "pll1_12"};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) void __init pxa910_clk_init(phys_addr_t mpmu_phys, phys_addr_t apmu_phys,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) phys_addr_t apbc_phys, phys_addr_t apbcp_phys)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) struct clk *uart_pll;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) void __iomem *mpmu_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) void __iomem *apmu_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) void __iomem *apbcp_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) void __iomem *apbc_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) mpmu_base = ioremap(mpmu_phys, SZ_4K);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) if (!mpmu_base) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) pr_err("error to ioremap MPMU base\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) apmu_base = ioremap(apmu_phys, SZ_4K);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) if (!apmu_base) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) pr_err("error to ioremap APMU base\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) apbcp_base = ioremap(apbcp_phys, SZ_4K);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) if (!apbcp_base) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) pr_err("error to ioremap APBC extension base\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) apbc_base = ioremap(apbc_phys, SZ_4K);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) if (!apbc_base) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) pr_err("error to ioremap APBC base\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) clk = clk_register_fixed_rate(NULL, "clk32", NULL, 0, 3200);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) clk_register_clkdev(clk, "clk32", NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) clk = clk_register_fixed_rate(NULL, "vctcxo", NULL, 0, 26000000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) clk_register_clkdev(clk, "vctcxo", NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) clk = clk_register_fixed_rate(NULL, "pll1", NULL, 0, 624000000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) clk_register_clkdev(clk, "pll1", NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) clk = clk_register_fixed_factor(NULL, "pll1_2", "pll1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) CLK_SET_RATE_PARENT, 1, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) clk_register_clkdev(clk, "pll1_2", NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) clk = clk_register_fixed_factor(NULL, "pll1_4", "pll1_2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) CLK_SET_RATE_PARENT, 1, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) clk_register_clkdev(clk, "pll1_4", NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) clk = clk_register_fixed_factor(NULL, "pll1_8", "pll1_4",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) CLK_SET_RATE_PARENT, 1, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) clk_register_clkdev(clk, "pll1_8", NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) clk = clk_register_fixed_factor(NULL, "pll1_16", "pll1_8",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) CLK_SET_RATE_PARENT, 1, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) clk_register_clkdev(clk, "pll1_16", NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) clk = clk_register_fixed_factor(NULL, "pll1_6", "pll1_2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) CLK_SET_RATE_PARENT, 1, 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) clk_register_clkdev(clk, "pll1_6", NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) clk = clk_register_fixed_factor(NULL, "pll1_12", "pll1_6",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) CLK_SET_RATE_PARENT, 1, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) clk_register_clkdev(clk, "pll1_12", NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) clk = clk_register_fixed_factor(NULL, "pll1_24", "pll1_12",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) CLK_SET_RATE_PARENT, 1, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) clk_register_clkdev(clk, "pll1_24", NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) clk = clk_register_fixed_factor(NULL, "pll1_48", "pll1_24",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) CLK_SET_RATE_PARENT, 1, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) clk_register_clkdev(clk, "pll1_48", NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) clk = clk_register_fixed_factor(NULL, "pll1_96", "pll1_48",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) CLK_SET_RATE_PARENT, 1, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) clk_register_clkdev(clk, "pll1_96", NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) clk = clk_register_fixed_factor(NULL, "pll1_13", "pll1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) CLK_SET_RATE_PARENT, 1, 13);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) clk_register_clkdev(clk, "pll1_13", NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) clk = clk_register_fixed_factor(NULL, "pll1_13_1_5", "pll1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) CLK_SET_RATE_PARENT, 2, 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) clk_register_clkdev(clk, "pll1_13_1_5", NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) clk = clk_register_fixed_factor(NULL, "pll1_2_1_5", "pll1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) CLK_SET_RATE_PARENT, 2, 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) clk_register_clkdev(clk, "pll1_2_1_5", NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) clk = clk_register_fixed_factor(NULL, "pll1_3_16", "pll1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) CLK_SET_RATE_PARENT, 3, 16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) clk_register_clkdev(clk, "pll1_3_16", NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) uart_pll = mmp_clk_register_factor("uart_pll", "pll1_4", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) mpmu_base + MPMU_UART_PLL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) &uart_factor_masks, uart_factor_tbl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) ARRAY_SIZE(uart_factor_tbl), &clk_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) clk_set_rate(uart_pll, 14745600);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) clk_register_clkdev(uart_pll, "uart_pll", NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) clk = mmp_clk_register_apbc("twsi0", "pll1_13_1_5",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) apbc_base + APBC_TWSI0, 10, 0, &clk_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) clk_register_clkdev(clk, NULL, "pxa2xx-i2c.0");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) clk = mmp_clk_register_apbc("twsi1", "pll1_13_1_5",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) apbcp_base + APBCP_TWSI1, 10, 0, &clk_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) clk_register_clkdev(clk, NULL, "pxa2xx-i2c.1");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) clk = mmp_clk_register_apbc("gpio", "vctcxo",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) apbc_base + APBC_GPIO, 10, 0, &clk_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) clk_register_clkdev(clk, NULL, "mmp-gpio");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) clk = mmp_clk_register_apbc("kpc", "clk32",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) apbc_base + APBC_KPC, 10, 0, &clk_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) clk_register_clkdev(clk, NULL, "pxa27x-keypad");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) clk = mmp_clk_register_apbc("rtc", "clk32",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) apbc_base + APBC_RTC, 10, 0, &clk_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) clk_register_clkdev(clk, NULL, "sa1100-rtc");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) clk = mmp_clk_register_apbc("pwm0", "pll1_48",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) apbc_base + APBC_PWM0, 10, 0, &clk_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) clk_register_clkdev(clk, NULL, "pxa910-pwm.0");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) clk = mmp_clk_register_apbc("pwm1", "pll1_48",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) apbc_base + APBC_PWM1, 10, 0, &clk_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) clk_register_clkdev(clk, NULL, "pxa910-pwm.1");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) clk = mmp_clk_register_apbc("pwm2", "pll1_48",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) apbc_base + APBC_PWM2, 10, 0, &clk_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) clk_register_clkdev(clk, NULL, "pxa910-pwm.2");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) clk = mmp_clk_register_apbc("pwm3", "pll1_48",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) apbc_base + APBC_PWM3, 10, 0, &clk_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) clk_register_clkdev(clk, NULL, "pxa910-pwm.3");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) clk = clk_register_mux(NULL, "uart0_mux", uart_parent,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) ARRAY_SIZE(uart_parent),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) apbc_base + APBC_UART0, 4, 3, 0, &clk_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) clk_set_parent(clk, uart_pll);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) clk_register_clkdev(clk, "uart_mux.0", NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) clk = mmp_clk_register_apbc("uart0", "uart0_mux",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) apbc_base + APBC_UART0, 10, 0, &clk_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) clk_register_clkdev(clk, NULL, "pxa2xx-uart.0");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) clk = clk_register_mux(NULL, "uart1_mux", uart_parent,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) ARRAY_SIZE(uart_parent),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) apbc_base + APBC_UART1, 4, 3, 0, &clk_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) clk_set_parent(clk, uart_pll);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) clk_register_clkdev(clk, "uart_mux.1", NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) clk = mmp_clk_register_apbc("uart1", "uart1_mux",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) apbc_base + APBC_UART1, 10, 0, &clk_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) clk_register_clkdev(clk, NULL, "pxa2xx-uart.1");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) clk = clk_register_mux(NULL, "uart2_mux", uart_parent,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) ARRAY_SIZE(uart_parent),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) apbcp_base + APBCP_UART2, 4, 3, 0, &clk_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) clk_set_parent(clk, uart_pll);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) clk_register_clkdev(clk, "uart_mux.2", NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) clk = mmp_clk_register_apbc("uart2", "uart2_mux",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) apbcp_base + APBCP_UART2, 10, 0, &clk_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) clk_register_clkdev(clk, NULL, "pxa2xx-uart.2");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) clk = clk_register_mux(NULL, "ssp0_mux", ssp_parent,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) ARRAY_SIZE(ssp_parent),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) apbc_base + APBC_SSP0, 4, 3, 0, &clk_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) clk_register_clkdev(clk, "uart_mux.0", NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) clk = mmp_clk_register_apbc("ssp0", "ssp0_mux",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) apbc_base + APBC_SSP0, 10, 0, &clk_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) clk_register_clkdev(clk, NULL, "mmp-ssp.0");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) clk = clk_register_mux(NULL, "ssp1_mux", ssp_parent,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) ARRAY_SIZE(ssp_parent),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) apbc_base + APBC_SSP1, 4, 3, 0, &clk_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) clk_register_clkdev(clk, "ssp_mux.1", NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) clk = mmp_clk_register_apbc("ssp1", "ssp1_mux",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) apbc_base + APBC_SSP1, 10, 0, &clk_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) clk_register_clkdev(clk, NULL, "mmp-ssp.1");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) clk = mmp_clk_register_apmu("dfc", "pll1_4",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) apmu_base + APMU_DFC, 0x19b, &clk_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) clk_register_clkdev(clk, NULL, "pxa3xx-nand.0");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) clk = clk_register_mux(NULL, "sdh0_mux", sdh_parent,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) ARRAY_SIZE(sdh_parent),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) apmu_base + APMU_SDH0, 6, 1, 0, &clk_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) clk_register_clkdev(clk, "sdh0_mux", NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) clk = mmp_clk_register_apmu("sdh0", "sdh_mux",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) apmu_base + APMU_SDH0, 0x1b, &clk_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) clk_register_clkdev(clk, NULL, "sdhci-pxa.0");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) clk = clk_register_mux(NULL, "sdh1_mux", sdh_parent,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) ARRAY_SIZE(sdh_parent),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) apmu_base + APMU_SDH1, 6, 1, 0, &clk_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) clk_register_clkdev(clk, "sdh1_mux", NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) clk = mmp_clk_register_apmu("sdh1", "sdh1_mux",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) apmu_base + APMU_SDH1, 0x1b, &clk_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) clk_register_clkdev(clk, NULL, "sdhci-pxa.1");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) clk = mmp_clk_register_apmu("usb", "usb_pll",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) apmu_base + APMU_USB, 0x9, &clk_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) clk_register_clkdev(clk, "usb_clk", NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) clk = mmp_clk_register_apmu("sph", "usb_pll",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) apmu_base + APMU_USB, 0x12, &clk_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) clk_register_clkdev(clk, "sph_clk", NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) clk = clk_register_mux(NULL, "disp0_mux", disp_parent,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) ARRAY_SIZE(disp_parent),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) apmu_base + APMU_DISP0, 6, 1, 0, &clk_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) clk_register_clkdev(clk, "disp_mux.0", NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) clk = mmp_clk_register_apmu("disp0", "disp0_mux",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) apmu_base + APMU_DISP0, 0x1b, &clk_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) clk_register_clkdev(clk, NULL, "mmp-disp.0");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) clk = clk_register_mux(NULL, "ccic0_mux", ccic_parent,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) ARRAY_SIZE(ccic_parent),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) apmu_base + APMU_CCIC0, 6, 1, 0, &clk_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) clk_register_clkdev(clk, "ccic_mux.0", NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) clk = mmp_clk_register_apmu("ccic0", "ccic0_mux",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) apmu_base + APMU_CCIC0, 0x1b, &clk_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) clk_register_clkdev(clk, "fnclk", "mmp-ccic.0");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) clk = clk_register_mux(NULL, "ccic0_phy_mux", ccic_phy_parent,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) ARRAY_SIZE(ccic_phy_parent),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) apmu_base + APMU_CCIC0, 7, 1, 0, &clk_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) clk_register_clkdev(clk, "ccic_phy_mux.0", NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) clk = mmp_clk_register_apmu("ccic0_phy", "ccic0_phy_mux",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) apmu_base + APMU_CCIC0, 0x24, &clk_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) clk_register_clkdev(clk, "phyclk", "mmp-ccic.0");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) clk = clk_register_divider(NULL, "ccic0_sphy_div", "ccic0_mux",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) CLK_SET_RATE_PARENT, apmu_base + APMU_CCIC0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) 10, 5, 0, &clk_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) clk_register_clkdev(clk, "sphyclk_div", NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) clk = mmp_clk_register_apmu("ccic0_sphy", "ccic0_sphy_div",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) apmu_base + APMU_CCIC0, 0x300, &clk_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) clk_register_clkdev(clk, "sphyclk", "mmp-ccic.0");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) }
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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