^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) * pxa1928 clock framework source file
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Copyright (C) 2015 Linaro, Ltd.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Rob Herring <robh@kernel.org>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Based on drivers/clk/mmp/clk-of-mmp2.c:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * Copyright (C) 2012 Marvell
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * Chao Xie <xiechao.mail@gmail.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * This file is licensed under the terms of the GNU General Public
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * License version 2. This program is licensed "as is" without any
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) * warranty of any kind, whether express or implied.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/of_address.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/spinlock.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <dt-bindings/clock/marvell,pxa1928.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include "clk.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include "reset.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define MPMU_UART_PLL 0x14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) struct pxa1928_clk_unit {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) struct mmp_clk_unit unit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) void __iomem *mpmu_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) void __iomem *apmu_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) void __iomem *apbc_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) void __iomem *apbcp_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) static struct mmp_param_fixed_rate_clk fixed_rate_clks[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) {0, "clk32", NULL, 0, 32768},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) {0, "vctcxo", NULL, 0, 26000000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) {0, "pll1_624", NULL, 0, 624000000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) {0, "pll5p", NULL, 0, 832000000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) {0, "pll5", NULL, 0, 1248000000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) {0, "usb_pll", NULL, 0, 480000000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) static struct mmp_param_fixed_factor_clk fixed_factor_clks[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) {0, "pll1_d2", "pll1_624", 1, 2, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) {0, "pll1_d9", "pll1_624", 1, 9, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) {0, "pll1_d12", "pll1_624", 1, 12, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) {0, "pll1_d16", "pll1_624", 1, 16, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) {0, "pll1_d20", "pll1_624", 1, 20, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) {0, "pll1_416", "pll1_624", 2, 3, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) {0, "vctcxo_d2", "vctcxo", 1, 2, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) {0, "vctcxo_d4", "vctcxo", 1, 4, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) static struct mmp_clk_factor_masks uart_factor_masks = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) .factor = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) .num_mask = 0x1fff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) .den_mask = 0x1fff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) .num_shift = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) .den_shift = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) static struct mmp_clk_factor_tbl uart_factor_tbl[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) {.num = 832, .den = 234}, /*58.5MHZ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) {.num = 1, .den = 1}, /*26MHZ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) static void pxa1928_pll_init(struct pxa1928_clk_unit *pxa_unit)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) struct mmp_clk_unit *unit = &pxa_unit->unit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) mmp_register_fixed_rate_clks(unit, fixed_rate_clks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) ARRAY_SIZE(fixed_rate_clks));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) mmp_register_fixed_factor_clks(unit, fixed_factor_clks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) ARRAY_SIZE(fixed_factor_clks));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) mmp_clk_register_factor("uart_pll", "pll1_416",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) pxa_unit->mpmu_base + MPMU_UART_PLL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) &uart_factor_masks, uart_factor_tbl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) ARRAY_SIZE(uart_factor_tbl), NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) static DEFINE_SPINLOCK(uart0_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) static DEFINE_SPINLOCK(uart1_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) static DEFINE_SPINLOCK(uart2_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) static DEFINE_SPINLOCK(uart3_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) static const char *uart_parent_names[] = {"uart_pll", "vctcxo"};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) static DEFINE_SPINLOCK(ssp0_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) static DEFINE_SPINLOCK(ssp1_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) static const char *ssp_parent_names[] = {"vctcxo_d4", "vctcxo_d2", "vctcxo", "pll1_d12"};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) static DEFINE_SPINLOCK(reset_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) static struct mmp_param_mux_clk apbc_mux_clks[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) {0, "uart0_mux", uart_parent_names, ARRAY_SIZE(uart_parent_names), CLK_SET_RATE_PARENT, PXA1928_CLK_UART0 * 4, 4, 3, 0, &uart0_lock},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) {0, "uart1_mux", uart_parent_names, ARRAY_SIZE(uart_parent_names), CLK_SET_RATE_PARENT, PXA1928_CLK_UART1 * 4, 4, 3, 0, &uart1_lock},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) {0, "uart2_mux", uart_parent_names, ARRAY_SIZE(uart_parent_names), CLK_SET_RATE_PARENT, PXA1928_CLK_UART2 * 4, 4, 3, 0, &uart2_lock},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) {0, "uart3_mux", uart_parent_names, ARRAY_SIZE(uart_parent_names), CLK_SET_RATE_PARENT, PXA1928_CLK_UART3 * 4, 4, 3, 0, &uart3_lock},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) {0, "ssp0_mux", ssp_parent_names, ARRAY_SIZE(ssp_parent_names), CLK_SET_RATE_PARENT, PXA1928_CLK_SSP0 * 4, 4, 3, 0, &ssp0_lock},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) {0, "ssp1_mux", ssp_parent_names, ARRAY_SIZE(ssp_parent_names), CLK_SET_RATE_PARENT, PXA1928_CLK_SSP1 * 4, 4, 3, 0, &ssp1_lock},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) static struct mmp_param_gate_clk apbc_gate_clks[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) {PXA1928_CLK_TWSI0, "twsi0_clk", "vctcxo", CLK_SET_RATE_PARENT, PXA1928_CLK_TWSI0 * 4, 0x3, 0x3, 0x0, 0, &reset_lock},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) {PXA1928_CLK_TWSI1, "twsi1_clk", "vctcxo", CLK_SET_RATE_PARENT, PXA1928_CLK_TWSI1 * 4, 0x3, 0x3, 0x0, 0, &reset_lock},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) {PXA1928_CLK_TWSI2, "twsi2_clk", "vctcxo", CLK_SET_RATE_PARENT, PXA1928_CLK_TWSI2 * 4, 0x3, 0x3, 0x0, 0, &reset_lock},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) {PXA1928_CLK_TWSI3, "twsi3_clk", "vctcxo", CLK_SET_RATE_PARENT, PXA1928_CLK_TWSI3 * 4, 0x3, 0x3, 0x0, 0, &reset_lock},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) {PXA1928_CLK_TWSI4, "twsi4_clk", "vctcxo", CLK_SET_RATE_PARENT, PXA1928_CLK_TWSI4 * 4, 0x3, 0x3, 0x0, 0, &reset_lock},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) {PXA1928_CLK_TWSI5, "twsi5_clk", "vctcxo", CLK_SET_RATE_PARENT, PXA1928_CLK_TWSI5 * 4, 0x3, 0x3, 0x0, 0, &reset_lock},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) {PXA1928_CLK_GPIO, "gpio_clk", "vctcxo", CLK_SET_RATE_PARENT, PXA1928_CLK_GPIO * 4, 0x3, 0x3, 0x0, 0, &reset_lock},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) {PXA1928_CLK_KPC, "kpc_clk", "clk32", CLK_SET_RATE_PARENT, PXA1928_CLK_KPC * 4, 0x3, 0x3, 0x0, MMP_CLK_GATE_NEED_DELAY, NULL},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) {PXA1928_CLK_RTC, "rtc_clk", "clk32", CLK_SET_RATE_PARENT, PXA1928_CLK_RTC * 4, 0x83, 0x83, 0x0, MMP_CLK_GATE_NEED_DELAY, NULL},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) {PXA1928_CLK_PWM0, "pwm0_clk", "vctcxo", CLK_SET_RATE_PARENT, PXA1928_CLK_PWM0 * 4, 0x3, 0x3, 0x0, 0, &reset_lock},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) {PXA1928_CLK_PWM1, "pwm1_clk", "vctcxo", CLK_SET_RATE_PARENT, PXA1928_CLK_PWM1 * 4, 0x3, 0x3, 0x0, 0, &reset_lock},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) {PXA1928_CLK_PWM2, "pwm2_clk", "vctcxo", CLK_SET_RATE_PARENT, PXA1928_CLK_PWM2 * 4, 0x3, 0x3, 0x0, 0, &reset_lock},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) {PXA1928_CLK_PWM3, "pwm3_clk", "vctcxo", CLK_SET_RATE_PARENT, PXA1928_CLK_PWM3 * 4, 0x3, 0x3, 0x0, 0, &reset_lock},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) /* The gate clocks has mux parent. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) {PXA1928_CLK_UART0, "uart0_clk", "uart0_mux", CLK_SET_RATE_PARENT, PXA1928_CLK_UART0 * 4, 0x3, 0x3, 0x0, 0, &uart0_lock},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) {PXA1928_CLK_UART1, "uart1_clk", "uart1_mux", CLK_SET_RATE_PARENT, PXA1928_CLK_UART1 * 4, 0x3, 0x3, 0x0, 0, &uart1_lock},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) {PXA1928_CLK_UART2, "uart2_clk", "uart2_mux", CLK_SET_RATE_PARENT, PXA1928_CLK_UART2 * 4, 0x3, 0x3, 0x0, 0, &uart2_lock},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) {PXA1928_CLK_UART3, "uart3_clk", "uart3_mux", CLK_SET_RATE_PARENT, PXA1928_CLK_UART3 * 4, 0x3, 0x3, 0x0, 0, &uart3_lock},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) {PXA1928_CLK_SSP0, "ssp0_clk", "ssp0_mux", CLK_SET_RATE_PARENT, PXA1928_CLK_SSP0 * 4, 0x3, 0x3, 0x0, 0, &ssp0_lock},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) {PXA1928_CLK_SSP1, "ssp1_clk", "ssp1_mux", CLK_SET_RATE_PARENT, PXA1928_CLK_SSP1 * 4, 0x3, 0x3, 0x0, 0, &ssp1_lock},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) static void pxa1928_apb_periph_clk_init(struct pxa1928_clk_unit *pxa_unit)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) struct mmp_clk_unit *unit = &pxa_unit->unit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) mmp_register_mux_clks(unit, apbc_mux_clks, pxa_unit->apbc_base,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) ARRAY_SIZE(apbc_mux_clks));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) mmp_register_gate_clks(unit, apbc_gate_clks, pxa_unit->apbc_base,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) ARRAY_SIZE(apbc_gate_clks));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) static DEFINE_SPINLOCK(sdh0_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) static DEFINE_SPINLOCK(sdh1_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) static DEFINE_SPINLOCK(sdh2_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) static DEFINE_SPINLOCK(sdh3_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) static DEFINE_SPINLOCK(sdh4_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) static const char *sdh_parent_names[] = {"pll1_624", "pll5p", "pll5", "pll1_416"};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) static DEFINE_SPINLOCK(usb_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) static struct mmp_param_mux_clk apmu_mux_clks[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) {0, "sdh_mux", sdh_parent_names, ARRAY_SIZE(sdh_parent_names), CLK_SET_RATE_PARENT, PXA1928_CLK_SDH0 * 4, 8, 2, 0, &sdh0_lock},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) static struct mmp_param_div_clk apmu_div_clks[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) {0, "sdh_div", "sdh_mux", 0, PXA1928_CLK_SDH0 * 4, 10, 4, CLK_DIVIDER_ONE_BASED, &sdh0_lock},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) static struct mmp_param_gate_clk apmu_gate_clks[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) {PXA1928_CLK_USB, "usb_clk", "usb_pll", 0, PXA1928_CLK_USB * 4, 0x9, 0x9, 0x0, 0, &usb_lock},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) {PXA1928_CLK_HSIC, "hsic_clk", "usb_pll", 0, PXA1928_CLK_HSIC * 4, 0x9, 0x9, 0x0, 0, &usb_lock},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) /* The gate clocks has mux parent. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) {PXA1928_CLK_SDH0, "sdh0_clk", "sdh_div", CLK_SET_RATE_PARENT, PXA1928_CLK_SDH0 * 4, 0x1b, 0x1b, 0x0, 0, &sdh0_lock},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) {PXA1928_CLK_SDH1, "sdh1_clk", "sdh_div", CLK_SET_RATE_PARENT, PXA1928_CLK_SDH1 * 4, 0x1b, 0x1b, 0x0, 0, &sdh1_lock},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) {PXA1928_CLK_SDH2, "sdh2_clk", "sdh_div", CLK_SET_RATE_PARENT, PXA1928_CLK_SDH2 * 4, 0x1b, 0x1b, 0x0, 0, &sdh2_lock},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) {PXA1928_CLK_SDH3, "sdh3_clk", "sdh_div", CLK_SET_RATE_PARENT, PXA1928_CLK_SDH3 * 4, 0x1b, 0x1b, 0x0, 0, &sdh3_lock},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) {PXA1928_CLK_SDH4, "sdh4_clk", "sdh_div", CLK_SET_RATE_PARENT, PXA1928_CLK_SDH4 * 4, 0x1b, 0x1b, 0x0, 0, &sdh4_lock},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) static void pxa1928_axi_periph_clk_init(struct pxa1928_clk_unit *pxa_unit)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) struct mmp_clk_unit *unit = &pxa_unit->unit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) mmp_register_mux_clks(unit, apmu_mux_clks, pxa_unit->apmu_base,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) ARRAY_SIZE(apmu_mux_clks));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) mmp_register_div_clks(unit, apmu_div_clks, pxa_unit->apmu_base,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) ARRAY_SIZE(apmu_div_clks));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) mmp_register_gate_clks(unit, apmu_gate_clks, pxa_unit->apmu_base,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) ARRAY_SIZE(apmu_gate_clks));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) static void pxa1928_clk_reset_init(struct device_node *np,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) struct pxa1928_clk_unit *pxa_unit)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) struct mmp_clk_reset_cell *cells;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) int i, base, nr_resets;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) nr_resets = ARRAY_SIZE(apbc_gate_clks);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) cells = kcalloc(nr_resets, sizeof(*cells), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) if (!cells)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) base = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) for (i = 0; i < nr_resets; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) cells[base + i].clk_id = apbc_gate_clks[i].id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) cells[base + i].reg =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) pxa_unit->apbc_base + apbc_gate_clks[i].offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) cells[base + i].flags = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) cells[base + i].lock = apbc_gate_clks[i].lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) cells[base + i].bits = 0x4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) mmp_clk_reset_register(np, cells, nr_resets);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) static void __init pxa1928_mpmu_clk_init(struct device_node *np)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) struct pxa1928_clk_unit *pxa_unit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) pxa_unit = kzalloc(sizeof(*pxa_unit), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) if (!pxa_unit)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) pxa_unit->mpmu_base = of_iomap(np, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) if (!pxa_unit->mpmu_base) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) pr_err("failed to map mpmu registers\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) kfree(pxa_unit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) pxa1928_pll_init(pxa_unit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) CLK_OF_DECLARE(pxa1928_mpmu_clk, "marvell,pxa1928-mpmu", pxa1928_mpmu_clk_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) static void __init pxa1928_apmu_clk_init(struct device_node *np)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) struct pxa1928_clk_unit *pxa_unit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) pxa_unit = kzalloc(sizeof(*pxa_unit), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) if (!pxa_unit)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) pxa_unit->apmu_base = of_iomap(np, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) if (!pxa_unit->apmu_base) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) pr_err("failed to map apmu registers\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) kfree(pxa_unit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) mmp_clk_init(np, &pxa_unit->unit, PXA1928_APMU_NR_CLKS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) pxa1928_axi_periph_clk_init(pxa_unit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) CLK_OF_DECLARE(pxa1928_apmu_clk, "marvell,pxa1928-apmu", pxa1928_apmu_clk_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) static void __init pxa1928_apbc_clk_init(struct device_node *np)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) struct pxa1928_clk_unit *pxa_unit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) pxa_unit = kzalloc(sizeof(*pxa_unit), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) if (!pxa_unit)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) pxa_unit->apbc_base = of_iomap(np, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) if (!pxa_unit->apbc_base) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) pr_err("failed to map apbc registers\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) kfree(pxa_unit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) mmp_clk_init(np, &pxa_unit->unit, PXA1928_APBC_NR_CLKS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) pxa1928_apb_periph_clk_init(pxa_unit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) pxa1928_clk_reset_init(np, pxa_unit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) CLK_OF_DECLARE(pxa1928_apbc_clk, "marvell,pxa1928-apbc", pxa1928_apbc_clk_init);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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